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6255B–ATARM–26-Jun-09
Application Note
2.2
NAND Flash vs. NOR Flash
The most important item for memories is the cost per bit which depends on memory cell area per
bit. The cell area of NAND Flash is smaller than that of NOR Flash, making the NAND Flash
more cost effective than NOR Flash.
The first significant difference between NAND and NOR Flash is the hardware interface.
2.2.1
Hardware Interface
NOR Flash has a fully memory-mapped random access interface similar to a RAM, with dedi-
cated address lines and data lines making it “bootable”.
NAND Flash uses a multiplexed I/O interface and additional control signals. It is controlled by
sending commands and addresses through an 8-bit or 16-bit bus to an internal command and
address register.
NOR Flash random-access interface typically composed of 41 pins:
– CE# - chip enable
– WE# - write enable
– OE# - output enable
– D[15:0] - data bus
– A[20:0] - address bus
– WP# - write protect
NAND Flash I/O device-type interface composed of up to 24 pins:
– CE# - chip enable
– WE# - write enable
– RE# - read enable
– CLE - command latch enable
– ALE - address latch enable
– I/O[7:0] or I/O[15:0] - data bus
– WP# - write protect
– R/B# - ready / busy
– RE - Read enable
2.2.2
Array Architecture
NOR Flash is divided into blocks which typically contain many 16-bit wide words. Random
access to stored data words is achieved by placing the selected word address on the address
bus and then reading that data off the data bus. Erase operations are managed at the block level
and words can be programmed after a block has been erased.
NAND Flash is also divided into blocks which contain many pages instead of words (2K +64
bytes). Read and program operations take place on a per-page basis whereas erase operations
takes place on a block basis.
To read or write from NAND Flash, a command sequence is issued to select a block and a page.
After this selection, the entire page can be read or written.
