7
6255B–ATARM–26-Jun-09
Application Note
5. AT91 EBI NandFlash Logic
The NAND Flash logic is driven by the Static Memory Controller (SMC) on the NCS3 address
space. Programming the CS3A field in the EBI_CSA Register in the Bus Matrix User Interface to
the appropriate value enables the NAND Flash logic. For details on this register, refer to the Bus
Matrix User Interface section in the product datasheet. Access to an external NAND Flash
device is then made by accessing the address space reserved to NCS3 (i.e., between
0x40000000 and 0x4FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE
and NANDWE signals when the NCS3 signal is active.(refer to the Static Memory Controller
section in the product datasheet).
The address latch enable and command latch enable signals on the NAND Flash device are
driven by address bits A22 and A21 of the EBI address bus.The command, address or data
words on the data bus of the NAND Flash device are distinguished by using their address within
the NCS3 address space. The chip enable (CE) signal of the device and the ready/busy (R/B)
signals are connected to PIO lines.
Two NAND Flash types exists, those who are “CE don’t care” and those who are not.
For “CE don’t care” NAND, the chip enable state is don’t care during the busy period preceding
the data read cycle. Thus allowing this flash to be connected to active memory buses such as
the AT91 memory bus.
For standard NAND, the CE signal remains asserted even when NCS3 is not selected, prevent-
ing the device from returning to standby mode. In this case, a PIO line should be dedicated to
drive the Chip Enable signal.
Unlike the AT91SAM9261, where A21 and A22 are not specifically dedicated to NAND flash
ALE and CLE signals, on the AT91SAM9260 A21/ALE and A22/CLE are the signals mandatory
to drive the NAND flash and ECC controller. Another combination of addresses prevent using
the ECC controller with the NAND Flash.
Notes: 1. Any free PIO can be used for this purpose
2. For standard NAND
3. For AT91SAM9261 the address bit A21 is arbitrarily dedicated to CLE
4. For AT91SAM9261 the address bit A22 is arbitrarily dedicated to ALE
Table 5-1.
EBI Signals Example for AT91SAM9261
Name
Function
Type
Active Level
NANDCS
NAND Flash Chip Select Line
Output
Low
NANDOE
NAND Flash Output Enable
Output
Low
NANDWE
NAND Flash Write Enable
Output
Low
CLE(A21) (3)
Command Latch Enable
Output
High
ALE(A22) (4)
Address Latch Enable
Output
High
PIOx/CE
Chip Enable (1)(2)
Output
Low
PIOy/RDY/BSY
Ready/Busy (1)
Input
Low
