Atmel AT91SAM9, Примечание к применению

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6255B–ATARM–26-Jun-09
Application Note
As CLE and ALE are address lines (A21, A22), an additional setup timing is required to respect
tAR (10 ns) and tCLR (10 ns) on STATUS or RANDOM DATA READ Cycle.
Table 6-4. NAND Flash Timings vs. SMC Configuration
Timing Name
Value (ns)
Min / Max
SMC Description for “CE don’t Care”
NAND
SMC Description for Standard
NAND
Value @
100 MHz
(cycles)
Setup
tCLS 25 NWE Setup + NWE Pulse N/A - CE is a PIO line 3
tALS 25 NWE Setup + NWE Pulse N/A - CE is a PIO line 3
tCS 35 NWE Setup + NWE Pulse N/A - CE is a PIO line 4
tDS 20 NWE Setup + NWE Pulse NWE Setup + NWE Pulse 2
tCEA 45 Not programmable Not programmable
tREA 30 Not programmable Not programmable
tRR 20 managed by software managed by software
Hold
tCLH 10 NWE Hold NWE Hold 1
tALH 10 NWE Hold NWE Hold 1
tCH 10 NWE Hold N/A - CE is a PIO line 1
tDH 10 Data Float Time Data Float Time 1
tOH 15 Data Float Time Data Float Time 2
tREH 15 NRD Cycle - NRD Pulse NRD Cycle - NRD Pulse 2
Pulse
tWP 25 NWE pulse length NWE pulse length 3
tRP 25 NRD pulse length NRD pulse length 3
tWC 45 NWE cycle NWE cycle 5
tRC 50 NRD cycle NRD cycle 5