74
32099DS–06/2010
AT32UC3L016/32/64
8.
Generic clock sources are kept running in sleep modes
If a clock is used as a source for a generic clock when going to a sleep mode where clock
sources are stopped, the source of the generic clock will be kept running. Please refer to the
Power Manager chapter for details about sleep modes.
Fix/Workaround
Disable generic clocks before going to sleep modes where clock sources are stopped to
save power.
9.
DFLL clock is unstable with a fast reference clock
The DFLL clock can be unstable when a fast clock is used as reference clock in closed loop
mode.
Fix/Workaround
Use the 32 KHz crystal oscillator clock or a clock with similar frequency as DFLLIF reference
clock.
10. DFLLIF indicates coarse lock too early
The DFLLIF might indicate coarse lock too early, the DFLL will lose coarse lock and regain it
later.
Fix/Workaround
Use max step size (DFLL0MAXSTEP.MAXSTEP) of 4 or higher.
11. DFLLIF dithering does not work
The DFLLIF dithering does not work.
Fix/Workaround
None.
12. SCIF VERSION register reads 0x100
The VERSION register reads 0x100 instead of 0x102.
Fix/Workaround
None.
13. DFLLVERSION register reads 0x200
The DFLLVERSION register reads 0x200 instead of 0x201.
Fix/Workaround
None.
14. RCCRVERSION register reads 0x100
The RCCRVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
15. OSC32VERSION register reads 0x100
The OSC32VERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
16. VREGVERSION register reads 0x100
The VREGVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
17. RC120MVERSION register reads 0x100
The RC120MVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
