392
(3)
Mode(0-7)
This sets the bit length and link format of the images to be output from
iTMDS. A setting which is independent of the bit length for pattern drawing
can be selected. It is also possible to select the bit length automatically. The
portion by which the bit length for pattern drawing exceeds the bit length
which has been set here is discarded. A deficient portion is filled with zeros.
When the dot clock frequency is in the range of 25 MHz to 165 MHz,
Single Link can be selected, and the data can be distributed to and output
from output channels 1 and 2.
When the dot clock frequency is in the range of 50 MHz to 330 MHz, Dual
Link can be selected, and the data can be distributed to and output from
output channels 1 and 2.
When the dot clock frequency is in the range of 297 MHz to 660 MHz,
Quad Link can be selected, and the data can be output using output
channels 1 and 2.
When the dot clock frequency is in the range of 594 MHz to 1320 MHz, by
selecting Octal Link and by using two output boards, the data can be
output by combining the data of board #1 output channels 1 and 2 and the
data of board #2 output channels 1 and 2.
0
Single (8bit)
The data is output by Single Link from output
channels 1 and 2. The portion by which the bit
length exceeds 8 bits is discarded. (Max. 12 bits
with the iTMDS format)
1
Dual (8bit)
The data is output by Dual Link from output
channels 1 and 2. The portion by which the bit
length exceeds 8 bits is discarded. (Max. 12 bits
with the iTMDS format)
2
Single (16bit)
The data is output by one connector using Master
and Slave links. It outputs max. 16-bit signal.
The portion by which the bit length for pattern
drawing is deficient from the bit length which has
been set here is filled with zeros. Master outputs
upper bits. Slave outputs lower bits.
3
Dual (16bit)
Up to 16 bits can be output by Dual Link using two
connectors. The portion by which the bit length for
pattern drawing is deficient from the bit length
which has been set here is filled with zeros.
4
Single (Auto)
The data is output by Single Link from output
channels 1 and 2.
Single (8 bits)
or
Single (16 bits)
is automatically selected depending on the bit length
for pattern drawing.
5
Dual (Auto)
The data is output by Single Link from output
channels 1 and 2.
Single (8 bits)
or
Single (16 bits)
is automatically selected depending on the bit length
for pattern drawing.
6
Quad (8bit)
The data is output by Quad Link using output
channels 1 and 2. The portion by which the bit
length for pattern drawing exceeds 8 bits is
discarded. (Max. 12 bits with the iTMDS)
For details on the screen splitting method, refer to
“Split” in the next section.
7
Octal (8bit)
By using two output boards, the data is output by
Octal Link by combining the data of board #1
output channels 1 and 2 and the data of board #2
output channels 1 and 2. The portion by which the
bit length for pattern drawing exceeds 8 bits is
discarded. (Max. 12 bits with the iTMDS format)
For details on the screen splitting method, refer to
“Split” in the next section.
Содержание VG-876
Страница 1: ...Video Signal Generator VG 876 Instruction Manual Ver 3 40 ...
Страница 2: ......
Страница 30: ...16 ...
Страница 57: ...Chapter 3 TIMING DATA SETTINGS 43 ...
Страница 103: ...Chapter 4 PATTERN SETTINGS 89 1 2 3 4 5 6 0 ...
Страница 134: ...120 GUI Display Selected port ...
Страница 135: ...Chapter 4 PATTERN SETTINGS 121 HEX Display Selected port ...
Страница 143: ...Chapter 4 PATTERN SETTINGS 129 ...
Страница 177: ...Chapter 6 HDCP SETTINGS AND EXECUTION 163 ...
Страница 205: ...Chapter 7 VG 876 SYSTEM SETTINGS 191 ...
Страница 223: ...Chapter 8 DATA COPYING ERASING 209 ...
Страница 237: ...Chapter 9 USEFUL FUNCTIONS 223 ...
Страница 312: ...298 Horizontally 2 split output Split Mode 0 2 select either one of them Data Transfer assignment Split Image ...
Страница 336: ...322 10 5 3 Data transfer method Normal MODE 2Lane output ...
Страница 338: ...324 Normal MODE 4Lane output ...
Страница 374: ...360 Assignment of each lane Lane 1 2 Lane 5 6 Lane 9 10 Lane 13 14 Lane 3 4 Lane 7 8 Lane 11 12 Lane 15 16 ...
Страница 376: ...362 Assignment of each lane ...
Страница 378: ...364 Assignment of each lane Lane 1 4 Lane 9 12 Lane 5 8 Lane 13 16 ...
Страница 380: ...366 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Страница 382: ...368 Assignment of each lane Lane1 8 Lane9 16 ...
Страница 384: ...370 Assignment of each lane Lane1 8 Lane9 16 ...
Страница 386: ...372 Assignment of each lane Lane1 8 Lane9 16 ...
Страница 388: ...374 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Страница 390: ...376 Assignment of each lane Lane1 4 Lane9 12 Lane5 8 Lane 13 16 ...
Страница 392: ...378 Assignment of each lane Lane1 16 ...
Страница 453: ...Chapter 10 INTERFACE SETTINGS 439 Connection figure of VM 1876 MX s ...
Страница 464: ...450 Reverse Mode Top Bottom Reverse Mode LR TB ...
Страница 465: ...Chapter 10 INTERFACE SETTINGS 451 Multi VGMode V4Div Vertical Split Reverse Mode No Reverse Reverse Mode Left Right ...
Страница 466: ...452 Reverse Mode Top Bottom Reverse Mode LR TB ...
Страница 467: ...Chapter 10 INTERFACE SETTINGS 453 Multi VGMode V2Div Vertically 2 split Reverse Mode No Reverse Reverse Mode Left Right ...
Страница 468: ...454 Reverse Mode Top Bottom Reverse Mode LR TB ...
Страница 495: ...Chapter 10 INTERFACE SETTINGS 481 2 When Video Width is 8 bit ...
Страница 496: ...482 3 When Video Width is 10 bit ...
Страница 501: ...Chapter 10 INTERFACE SETTINGS 487 2 When iTMDS output ...
Страница 504: ......
Страница 538: ...524 ...