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Chapter 4
INTERFACE SETTINGS
141
Specifications of bit assignment during 16-bit (8 + 8 bits) output
DVI multiple bit output
Sixteen bits are output by using two DVI channels and outputting the data using 8 + 8 bits.
The higher 8 bits are allocated to one channel and the lower 8 bits to the other channel.
If the setting involves 15 or fewer bits, “0” is entered for the lower bits which will not be used.
iTMDS multiple bit output
When outputting multiple bits using the iTMDS format, select iTMDS as the output setting.
When iTMDS has been selected, the multiple-bit output mode (10 bits or 12 bits) which uses one iTMDS channel
is automatically tracked in tandem with the number of output bits regardless of which bit mode was selected.
* The 8 + 8 bit multi-channel output mode takes effect only when DVI has been selected as the output setting. If
iTMDS has been selected, the multiple-bit output mode (10 bits or 12 bits) which uses one iTMDS channel is
automatically tracked in tandem with the number of output bits regardless of which bit mode was selected.
* As shown in the figure below, what is output as the data of channels 1 to 4 for the Master and Slave of Dual Link
of VM-1824 is described in this section.
* Also described below in this section is the Single Link data of the VM-1824-A which is output as the data of
channels 1 to 4.
RGB 8Bit
[7:0]
RGB 8Bit
[7:0]
RGB 8Bit
[15:8]
RGB 8Bit
[15:8]
Link0
Link1
Link2
Link3
Link4
Link5
1CH
2CH
2CH
Connector
3CH
4CH
【16(8+8) Bit 出力 SingleLink】
Dual
Link
Master
Dual
Link
Master
Dual
Link
Srave
Dual
Link
Srave
Link0
Link1
Link2
Link3
Link4
Link5
1CH
Connector
RGB 8Bit
[7:0]
RGB 8Bit
[15:8]
RGB 8Bit
[7:0]
RGB 8Bit
[15:8]
Link0
Link1
Link2
Link3
Link4
Link5
1CH
2CH
2CH
Connector
3CH
4CH
Dual
Link
Master
Dual
Link
Master
Dual
Link
Srave
Dual
Link
Srave
Link0
Link1
Link2
Link3
Link4
Link5
1CH
Connector
【16(8+8) Bit 出力 DualLink】
[16-bit (8+8) output Single Link]
[16-bit (8+8) output Dual Link]
Содержание VG-870B
Страница 1: ...Programmable Video Signal Generator VG 870B 871B 873 874 Instruction Manual Ver 3 80 ...
Страница 2: ......
Страница 4: ......
Страница 14: ...x ...
Страница 58: ...40 ...
Страница 220: ...202 4 12 8 DDC CI For further details on the setting procedure refer to 6 13 4 DDC CI ...
Страница 229: ...Chapter 4 INTERFACE SETTINGS 211 Set LFE Playback Level 0 Unknown 1 0dB Playback 12 LFE PB Level 2 10dB Playback ...
Страница 286: ...268 ...
Страница 300: ...282 7 Interval 0 to 60 Interval The interval at which the V chip data is transmitted is set in 1 second increments ...
Страница 362: ...344 0 1 2 3 4 5 6 ...
Страница 394: ...376 ...
Страница 426: ...408 ...
Страница 450: ...432 ...
Страница 537: ...Chapter 11 SPECIFICATIONS 519 F0H letters me 1 F1H letters me 2 VESA specifications ...
Страница 538: ...520 F2H Chinese character AI F3H Chinese character BI ...
Страница 539: ...Chapter 11 SPECIFICATIONS 521 F4H Chinese character TAKA F5H Chinese character KIRI ...
Страница 540: ...522 F6H Chinese character KEN F7H Burst ...
Страница 541: ...Chapter 11 SPECIFICATIONS 523 11 3 4 Character pattern data 5 7 character pattern table 1 of 2 ...
Страница 542: ...524 5 7 character pattern table 2 of 2 ...
Страница 543: ...Chapter 11 SPECIFICATIONS 525 7 9 character pattern table 1 of 2 ...
Страница 544: ...526 7 9 character pattern table 2 of 2 8 9 dots are used for 80H to 8FH ...
Страница 545: ...Chapter 11 SPECIFICATIONS 527 16 16 character pattern table 1 of 4 ...
Страница 546: ...528 16 16 character pattern table 2 of 4 ...
Страница 547: ...Chapter 11 SPECIFICATIONS 529 16 16 character pattern table 3 of 4 ...
Страница 548: ...530 16 16 character pattern table 4 of 4 ...
Страница 554: ...536 ...