Model 8640B
TM 9-4935-601-14-7&P
SERVICE SHEET 20
PRINCIPLES OF OPERATION
General
The counter has two modes of operation:
1) COUNT: The counter counts the input frequency.
2) PHASE LOCK: The counter finishes the current count sequence, stores the count, then enters
phase lock counting down from the stored count to zero in a free-running mode.
The frequency is displayed on a six-digit LED numeric display.
Counter Operation - Count Mode (A8A2)
When COUNTER MODE LOCK switch S1 is out (Off) the count sequence is as follows: When the TIME
BASE line is high, decade counters U24 through U19 count the input pulses. When TIME BASE goes low,
the count is inhibited, the counter outputs are transferred to the outputs of storage buffers U7 through U12
which in turn drive the numeric displays A8A4U1 to U6. The storage buffer outputs are latched, and then
the counters are cleared. When TIME BASE goes high, the count begins again.
Shaping and Input Gating
Gates U15A, U2B, U2C, U14D, and U13A shape the input waveform into pulses of about 30 nanoseconds
duration. The circuit uses gate delays and positive feedback to shape the pulses. NAND gate U2D inhibits
the input to the counter when TIME BASE is low. D flip-flop U1A and gates U14B and U15B also shape the
input pulses and further assure that the pulse is either of full duration or is absent in the event that TIME
BASE goes low while an input pulse is high.
The output of gate U17C is normally low, and the output of gate U16B is normally high (the resistor R45
and inductor L1 hold the inputs low). When the TIME BASE goes low, the output of inverter U4E goes high.
The output of U16B goes low until resistor R45 discharges capacitor C10 and the output returns to a high.
While U16B is low, the low enable (EN) inputs of the storage buffers allow the data inputs to transfer to the
outputs. When the output of U16B goes high. the output of U17C goes high until inductor L1 charges C11
and the output returns to a low. While U17C is high, the counters are cleared. When TIME BASE goes
high, the outputs of U16B and U17C remain unchanged.
Overflow Detector
The overflow detector lights OVER FLOW lamp A8A4DS2 whenever a carry is generated by counter U19,
in which case the count has exceeded the number of digits available in the display. The output of inverter
U4B is normally high. Counter U14 generates a low at the carry (CRY) output on the count of nine, but the
output of U4B remains high. At the count of ten, the carry output of U14 returns high, output of U4B goes
low until resistor R49 discharges capacitor C14 and the output returns to a high. While U4B is low, D flip-
flop U5A clears. Shortly after TIME BASE goes low, the output of U16B goes high and toggles D flip-flop
U5B. If a low was present at the D input, the Q output goes high, turns on transistor Q16, and lights the
OVER FLOW lamp; otherwise Q remains low. When the TIME BASE goes high, the Q output of U5A goes
(or remains) high, and remains so until an overflow carry is generated.
Counter Operation - Phase Lock Mode (A8A2)
When COUNTER MODE LOCK switch SI is in (ON) the count just prior to the acquisition of phase lock is
transferred to the storage buffers U7 through U12 and then the buffers are latched. The decade counters
U19 to U24 then count the input pulses, counting down from the count stored in the buffers.
The count sequence is as follows: The count proceeds down to zero, then to 999,999, generating a borrow
output in U19. The borrow causes the Stall Counter decade counter U28 with D flip-flop U1B to be cleared
from its normal nine count and the main counters to be preset from the Storage Buffers. The input to the
main counter is inhibited while the input to the Stall Counter is enabled. The Stall Counter then begins
counting up. At the count of four, a high is generated at the output QC of the Stall Counter which clocks the
count-down input of the second counter U23 which subtracts ten from the count. When the Stall Counter
reaches the count of nine, the clock to the main counter is enabled and the clock to the
Stall Counter is disabled. The count proceeds down until a zero count is reached and the sequence
repeats.
In summary, the counter counts down to zero, then to 999,999, and then is preset to the stored count where
it remains for four more clock pulses. A count pulse into the second counter then subtracts ten from the
preset count. Finally, when a total of nine pulses has been counted by the Stall Counter, the main counter
starts counting down towards zero. The stall of nine counts gives the main counters adequate time to
preset. The nine count delay plus the count to one below zero (i.e., to 999,999) is compensated for by
subtracting ten from the main counter.
The circuit implementation of the sequence is as follows: When the count reaches 000,000, the borrow
(BRW) output of U19 goes low. The count proceeds to 999,999 at which time the borrow output goes high.
Normally, the input to inverter U4A is held low by inductor L2. The high at the borrow output of U19 is ac
coupled through capacitor C12 to the inverter and also the clear (CLR) input of the Stall Counter U28. The
inputs are held high long enough to clear U28 and flip-flop U1B. The Q output of U1B goes high and
inhibits the input to the main counter by means of OR gate U14C and enables the Stall Counter by means
of AND gate U17B. When counter U28 reaches a count of four, output QC goes high and the output of
NAND gate U2A goes low. The borrow output of counter, U24 is high because the count down (CD) input is
held high by
U14C. The low from the output of U2A causes a low at the output of U13C and also U13D. Since the
output of U14C is high, the output of NOR gate U25A is low. The low from U13D causes a high at the
output of NOR gate U25B and clocks the count down (CD) input of U23 once. If U23 is at a zero count, its
borrow output clocks counter U22. If U22 is at zero, it clocks counter U21, etc. When Stall Counter U28
reaches the count of eight, output QD goes high and causes a high on the D input of flip-flop U1B. The
next clock causes the Q output of U1B to go low which inhibits the clock to the Stall Counter and enables
the clock to the main counter.
In the normal count down mode, decade counters U19 to U24 form a synchronous counter. OR gates
U27A to U27C and AND gate U13C have high outputs unless all previous counters are at the zero count.
When any of the OR gates (or AND gate U13C) are low, the output of the following NOR gate (U5A to
U5D or U25B) goes high on the next clock input. Thus each counter changes count only at the
occurrence of a clock input and only if all previous counters are zero (their borrows having rippled through
to enable it).
Counter Operation - Transition from Counter Mode to Phase Lock Mode (A8A2)
When COUNTER MODE LOCK switch S1 is depressed (to ON) the counter sequences as follows:
Counters U19 to U24 continue counting up until TIME BASE goes low. Stall Counter U28 has been preset
to the count of eight, Storage Buffers U7 through U12 are loaded with the outputs of the counters and then
latched; then the counters are cleared and the input to the main counter is inhibited while the input to the
Stall Counter is enabled. The lock mode is now entered with LOCK high, and the QD output of stall
counter U28 high. The D input of U1B is high and the next clock input toggles the Q output to a low. The
clock to the main counter is then enabled and that to the Stall Counter disabled. The next input pulse
sends the main counter to 999,999 since it was previously cleared to zero. The counter now sequences in
the normal phase lock mode.
Flash Oscillator (A8A2)
When a phase lock error is detected, a 2 Hz flash oscillator is turned on to blink the display. Transistors
Q5 and Q4 form a two-stage astable multivibrator. A high on the ERROR line holds collector resistor R42
at about 3V, and the oscillator is biased on. The frequency of oscillation is determined by the time
constants of R39, C9 and R41, C8. The collector of Q4 switches transistor Q3 which switches the Vcc
supply to the Storage Buffers U7 through U12. With an open at the Vcc Supply, the Storage Buffer
outputs are open which represents a high to each display input. The displays generate a blank when all
inputs are high. When no error exists Q3 is held on by Q4 which is also on, and Vcc is at 5V.
TROUBLESHOOTING
It is assumed that a problem has been isolated to the up/down counter and display circuits as a result of
using the troubleshooting block diagrams. Troubleshoot by using the test equipment listed below,
performing the initial test conditions and control settings, and following the procedures outlined in the
table.
NOTE
The following tests depend upon the counter RF scaler circuits (shown on Service
Sheet 18) and the counter time base circuits (shown on Service Sheet 19) working
correctly.
Test Equipment
Digital Voltmeter .............................................................................................................. HP 3480B/3484A
Oscilloscope............................................................................................................HP 180A/1801A/1820C
Frequency Counter......................................................................................................................HP 5327C
Test Oscillator ............................................................................................................................... HP 652A
Initial Test Conditions
Top cover removed (see Service Sheet F for removal procedure). A8 Counter/Lock Assembly casting
cover removed and A8A2 Counter/Lock Board Assembly removed and extended for service (see Service
Sheet B for procedures). Connect the test oscillator 50-ohm output to COUNTER INPUT; set it for 500
mVrms.
Initial Control Settings
COUNTER MODE:
EXPAND.............................................................................................................. Off
LOCK .................................................................................................................. Off
Source ................................................................................................... EXT 0 - 550
RANGE .................................................................................................................................... 0.5 -1 MHz
FREQUENCY TUNE .....................................................................................................................Full ccw
RF ON/OFF ......................................................................................................................................... ON
NOTE
If in LOCK mode the frequency at RF OUTPUT differs by one count in the least
significant digit from the frequency indicated on the display ( 1 ambiguity of the
counter), the problem is probably caused by the total gate delays in the lock
circuit. Replace A8A2U14.
If the counter won't phase lock on a certain count in a certain digit, but will lock on
all other counts displayed by that digit, replace that digit's up/down counter.
Counter Time Base (A8A3, A9)
SERVICE SHEET 19
Up/Down Counter and Display Troubleshooting
Component
Test Conditions and
Normal Indication
If Indication
or Circuit
Control Settings
is Abnormal
SHAPING (A8A2)
Initial conditions and settings.
Pulse width at U13A pin 3
Check U2, U13, U14, U15,
Set COUNTER MODE to
>25 ns (high going pulse)
and associated circuitry
EXT 0 - 10 MHz.
INPUT GATING
Initial conditions and settings.
Pulse width at U15B pin 6
Check U1, U2, U14, U15
(A8A2)
Set COUNTER MODE to
>25 ns (low going pulse)
EXT O - 10 MHz.
COUNTERS,
Initial conditions and settings.
Each Display digit capable
Check Counter and circuitry
STORAGE
Ground TP2 to enable Storage
of being cycled up from
associated with faulty
BUFFERS
Buffers. Vary test oscillator
0 - 9
digit
(A8A2), AND
frequency.
DISPLAY (A8)
Ground TP4 (shown on
Each Display digit capable
Service Sheet 21) to disable
of being cycled down from
Flash Oscillator and phase
9 - 0
lock error signal. Then set
COUNTER MODE LOCK
to ON and vary test oscillator
frequency.
STALL
Initial conditions and settings
Display count counts down
Check U1B, U2, U13, U25,
COUNTER
(with test points ungrounded).
to 000000 (incrementing
U28, and associated
(A8A2)
Set test oscillator frequency
1 count per input cycle -
circuitry
to 64 Hz then: Ground TP2;
1 Hz). When count reaches
Ground TP4; Set COUNTER
000000, the following will
MODE LOCK to ON.
happen
NOTE
Input
TPA
Display
Cycle
(U28-6)
Count
Increase test oscillator fre-
quency to set display count to
1
Low
999999
000010 then reset frequency
2
Low
999999
to 64 Hz
3
Low
999999
You can also use a Logic Pulser
4
Low
999999
(such as HP 10526T) to inject
5
High
999989
pulses into XA8A5 pin 16 (i.e.,
6
High
999989
the input to U15A)
7
High
999989
8
High
999989
8
High
999989
9
Low
999989
10
Low
999989
11
Low
999988
12
Low
999987
NOTE
0
The count has reached 000000
1
The main counter underflows to 999999 and presets to the displayed count (i.e., 999999)
2-4
The main counter holds at 999999 while the stall counter counts 1, 2, 3
5
On count 4 of the stall counter, the main counter's second decade counts down by one
(i.e., the display is 999989)
6-10
The counter holds at 999989 while the stall counter counts 5, 6, 7, 8, 9
11 on
The main counter counts down normally
OVERFLOW
Initial conditions and settings
OVER FLOW lamp lit
Check U5, Q18,
DETECTOR
(with test points ungrounded).
A8A4DS2, and associated
(A8A2)
Set COUNTER MODE to
circuitry
INT and EXP X100.
FLASH
Initial conditions and settings.
Display flahses at approx-
Check Q3-5, U3, U16
OSCILLATOR
Set COUNTER MODE to
imately a 2 Hz rate and
(SS 21) and associated
(A8A2)
INT, LOCK to ON, and turn
digits count up as FRE-
circuitry
FREQUENCY TUNE cw.
QUENCY TUNE is
turned cw
8-58
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