Artesyn Embedded Technology ATCA-7365-CE, Инструкция по установке и эксплуатации

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Maps and Registers
ATCA-7365-CE Installation and Use (6806800L73N )
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6.3.1 Register Decoding
The FPGA registers may be accessed from the host or the IPMC. The host uses the LPC bus
interface and the IPMC uses an SPI interface.
6.3.1.1 LPC Decoding
The LPC bus supports different protocols.
6.3.1.1.1 LPC I/O Decoding
The LPC interface responds to LPC I/O accesses listed in Table "LPC I/O Register Map Overview"
on page 158 . All other LPC I/O accesses are ignored.
All LPC I/O accesses to address POSTCODE, within the address range REGISTERS and within the
address ranges of COM1 or COM2 (only when enabled during Super IO configuration) are
decoded by the LPC core.
6.3.1.1.2 LPC Memory Decoding
The LPC interface never responds to LPC Memory accesses.
6.3.1.1.3 LPC Firmware Decoding
The LPC interface never responds to LPC Firmware accesses.
Table 6-6 LPC I/O Register Map Overview
Base Address
Address
Size Address Range
Name
Description
0x4E 2 SIW Super IO Configuration Registers for Index and
Date
0x80 1 POSTCODE POST Code Register
BASE1 8 COM1 UART1. Serial Port 1 (Logical Device 4). BASE1
address is set up during Super IO Configuration.
BASE2 8 COM2 UART2. Serial Port 2. (Logical Device 4). BASE2
address is set up during Super IO Configuration.
0x600 128 REGISTERS FPGA Registers