Artesyn Embedded Technology ATCA-7365-CE, Инструкция по установке и эксплуатации

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Maps and Registers
ATCA-7365-CE Installation and Use (6806800L73N)
157
6.3 Registers
For register description, the convention is shown in Table "Register Default" on page 157 and
Table "Register Access Type" on page 157 .
Table 6-4 Register Default
Default Description
- Not applicable or undefined
0 or 1 Default value after PWR_GOOD is valid or after ICH_PLTRST
deassertion.
Undef. Undefined value
<reset>: 0 or 1 Default value after deassertion of the reset signal <reset>.
Ext. External Reset Source. Default depends on external logic level.
Table 6-5 Register Access Type
Access Description
r Read only
w Write only
r/w Read and write
w1c Write-1-to-clear, ignore bit while reading
r/w1c Read and write-1-to-clear, write 0 has no effect
r/w1s Read and write-1-to-set, write 0 has no effect
r/w1t Read and write-1-to-toggle, write 0 has no effect
LPC: The prefix “LPC:” signals that the access is restricted to the LPC
interface.
For example, LPC: r/w means that the register bit is read/writable
from the LPC interface.
IPMC: The prefix “IPMC:” signals that the access is restricted to the IPMC
SPI interface.
For example, IPMC: r/w means that the register bit is read/writable
from IPMC SPI interface.