1-1
CHAPTER 1
INTRODUCTION TO THE SBC5206 BOARD
1.1 INTRODUCTION
The SBC5206 is a versatile single board computer based on MCF5206 ColdFire Processor. It may be
used as a powerful microprocessor based controller in a variety of applications. With the addition of a
terminal, it serves as a complete microcomputer for development/evaluation, training and educational use.
The user must only connect an RS-232 compatible terminal (or a personal computer with terminal
emulation software) and a power supply to have a fully functional system.
Provisions have been made to connect this board to additional user supplied boards, via the
Microprocessor Expansion Bus connectors, to expand memory and I/O capabilities. Additional boards
may require bus buffers to permit additional bus loading.
Furthermore, provisions have been made in the PC-board to permit configuration of the board in a way
which best suits an application. Options available are: up to 32M of DRAM, Timer, I/O, ISA bus
interface, and up to 1M bytes of Flash or 2M bytes of EPROM. In addition, all of the I/O functions of the
MCF5206 are available for the user.
1.2 GENERAL HARDWARE DESCRIPTION
The SBC5206 board provides the RAM, Flash ROM, optional Ethernet interface (ISA bus), RS232, and
all the built-in I/O functions of the MCF5206 for learning and evaluating the attributes of the MCF5206.
The MCF5206 is a member of the ColdFire family of processors. It is a 32-bit processor with 32 bits of
addressing and 32 lines of data. The processor has eight 32-bit data registers, eight 32-bit address
registers, a 32-bit program counter, and a 16-bit status register.
The MCF5206 has a System Integration Module referred to as SIM. The module incorporates many of
the functions needed for system design. These include programmable chip-select logic, System
Protection logic, General purpose I/O, and Interrupt controller logic. The chip-select logic can select up
to eight memory banks or peripherals in addition to two banks of DRAM’s. The chip-select logic also
allows programmable number of wait-state to allow the use of slower memory (refer to MCF5206 User's
Manual by Motorola for detail information about the SIM.) The SBC5206 only uses four of the chip
selects to access the Flash ROM’s, MC68HC901, ISA bus interface, and the IACK for MC68HC901.
The DRAM controller is used to control one SIMM module of up to 32M bytes of DRAM, both -RAS
lines are used. All other functions of the SIM are available to the user.
A hardware watchdog timer (Bus Monitor) circuit is included in the SIM which monitors the bus
activities. If a bus cycle is not terminated within a programmable time, the watchdog timer will assert an
internal transfer error signal to terminate the bus cycle. A block diagram of the board is shown in Figure
1.1.
