ii
2.4.18 RESET - Reset the board and dBUG ................. 2-24
2.4.19 SET - Set Configuration .......................... 2-25
2.4.20 SHOW - Show Configuration ........................ 2-27
2.4.21 STEP - Step Over ................................. 2-28
2.4.22 SYMBOL - Symbol Name Management .................. 2-29
2.4.23 TRACE - Trace Into ............................... 2-30
2.4.24 UPDBUG - Update the dBUG Image ................... 2-31
2.4.25 UPUSER - Update User Code In Flash ............... 2-32
2.4.26 VERSION - Display dBUG Version ................... 2-33
2.5 TRAP #15 Functions ................................... 2-34
2.5.1 OUT_CHAR ......................................... 2-34
2.5.2 IN_CHAR .......................................... 2-34
2.5.3 CHAR_PRESENT ..................................... 2-35
2.5.4 EXIT_TO_dBUG ..................................... 2-35
CHAPTER 3 HARDWARE DESCRIPTION AND RECONFIGURATION .......... 3-1
3.1 THE PROCESSOR AND SUPPORT LOGIC ...................... 3-1
3.1.1 The Processor .................................... 3-1
3.1.2 The Reset Logic .................................. 3-1
3.1.3 The -HIZ Signal .................................. 3-2
3.1.4 The Clock Circuitry .............................. 3-2
3.1.5 Watchdog Timer (BUS MONITOR) ..................... 3-2
3.1.6 Interrupt Sources ................................ 3-2
3.1.7 Internal SRAM .................................... 3-3
3.1.8 The MCF5206 Registers and Memory Map ............. 3-3
3.1.9 Reset Vector Mapping ............................. 3-4
3.1.10 -TA Generation ................................... 3-4
3.1.11 Wait State Generator ............................. 3-5
3.2 THE DRAM SIMM ... .................................... 3-5
3.3 THE EPROM/FLASH ROM .................................. 3-5
3.4 THE SERIAL COMMUNICATION CHANNELS..................... 3-7
3.4.1 The MCF5206 DUART................................. 3-7
3.4.2 MC68HC901 ........................................ 3-7
3.4.3 Motorola Bus (M-Bus) Module ...................... 3-7
3.5 THE PARALLEL I/O PORT................................. 3-7
3.6 THE ISA BUS LOGIC .................................... 3-8
3.7 THE CONNECTORS AND THE EXPANSION BUS ................. 3-8
3.7.1 The Programming Connector J1 ..................... 3-8
3.7.2 The ISA Bus Auxiliary Power Connector J2 ......... 3-8
3.7.3 The Power Supply Connector J3 and J4 ............. 3-9
3.7.4 The Terminal Connector J5 ........................ 3-9
3.7.5 The Auxiliary Communication Connector J6 ......... 3-10
3.7.6 The Processor Expansion Bus J7, J9, and J10 ...... 3-10
3.7.6 The Debug Connector J8 ........................... 3-10
3.7.8 The ISA Bus Connector P1 ......................... 3-10
3.8 THE SBC5206 JUMPERS ................................... 3-16
APPENDIX A NETWORK DOWNLOAD ................................. A-1
A.1 Configuring dBUG for Network Downloads ................ A-1
A.1.1 Required Network Parameters ...................... A-1
A.1.2 Configuring dBUG Network Parameters .............. A-2
A.1.3 Troubleshooting Network Problems ................. A-2
