5
3.1.10 Wait State Generator
The Flash ROM and SRAM chips on the board may require some adjustments on the cycle time of the
processor to make them compatible with processor speed. To extend the CPU bus cycles for the slower
devices, the chip-select logic of the MCF5204 can be programmed to generate the -DTACK after a given
number of wait states. Refer to Sections 3.2 and 3.3 information about wait state requirements of SRAM’s
and Flash ROM’s respectively.
3.2 THE EXTERNAL SRAM
The SBC5204 has two 32-pin sockets (U11 and U12) for static RAM’s. These sockets support both the
128Kx8 (such as KM681000BLP) and 512Kx8 (such as HM628512). The board may be configured for
256K and 1M bytes of SRAM’s. The dBUG will detect the total memory installed on power-up.
The are two memory configuration choices:
a.
256K bytes -
For 256K bytes, install two 128Kx8 SRAM chips in U11 and U12. The memory
address range will be $00000000-$0003FFFF. The jumper JP2 pins 2 and 4 should be connected
(default).
b. 1
M bytes -
For 1M bytes, install two 512x8 SRAM chips in U11 and U12. The memory address
range will be $00000000-$000FFFFF. The jumper JP2 pins 4 and 6 should be connected.
The debugger programs the chip-select to generate one wait state for the SRAM.
1
2
3
4
5
6
JP2
3.3 THE EPROM/ FLASH ROM
There are two sockets for EPROM’s/Flash ROM’s on the SBC5204, U13 (high, even byte) and U14 (low,
odd byte). These sockets support 32K, 64K, 128K, 256K, 512K, and 1M-byte EPROM’s such as
27C256, 27C512, 27C010, 27C020, 27C040, and 27C080 chips for a total of up to 2M bytes. The
sockets also support the Flash ROM’s such as 29F010 and 29F040 which are 5-volt only devices.
If the user wishes to modify the size or the type of the memory chips, the jumpers JP2, JP3, and JP4
should be modified to accommodate different size and type of memory chips. Refer to Figure 3.1 for
jumper selection.
The board is shipped with two 29F010, 128K-byte, FLASH ROM’s for a total of 256K bytes. The first
128K of the Flash contains dBUG firmware. The second half (last 128K) is available to the user. The
high byte (even address) chip is installed in U13 socket and the low byte (odd address) chip is installed in
U14 socket. The chip-select signal generated by the MCF5204 (-CS0) enables both chips.
The MCF5204 chip-select logic can be programmed to generate the -DTACK for -CS0 signal after a
certain number of wait states. The dBUG programs this parameter to three wait-states.
