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3.1.2.1 The ATS/BUSW Line
The ATS/BUSW line can be configure to function as -ATS or BUSW after reset. If the -IRQ0 is kept low
during Reset, the pin is -ATS otherwise, it is BUSW. The SBC5204 leaves the -IRQ0 high during the
reset which chooses the BUSW function. If the -ATS function is needed, the user may press the ABORT
button (BLACK) while pressing the RESET button (RED) which will cause the -IRQ0 t remain low when
resetting the board and the -ATS function will be selected.
3.1.3 The Clock Circuitry
The SBC5204 uses a 25MHZ oscillator (U3) to provide the clock to CLK pin of the processor. This clock
also feeds to LSI2032 for its internal use and to produce clock for the ISA timings and MC68HC901 (1/4
system clock).
3.1.4 Watchdog Timer (BUS MONITOR)
A bus cycle is initiated by the processor providing the necessary information for the bus cycle (e.g. address,
data, control signals, etc.) and asserting the -CS low. Then, the processor waits for an acknowledgment (-
DTACK signal) from the addressed device before it can complete the bus cycle. It is possible (due to
incorrect programming) that the processor attempts to access part of the address space which physically
does not exist. In this case, the bus cycle will go on for ever, since there is no memory or I/O device to
provide an acknowledgment signal, and the processor will be in an infinite wait state. The MCF5204 has
the necessary logic built into the chip to watch the duration of the bus cycle. If the cycle is not terminated
within the preprogrammed duration the logic will internally assert Transfer Error signal. In response, the
processor will terminate the bus cycle and an access fault exception (trap) will take place.
The duration of the Watchdog is selected by BMT0-1 bits in System Protection Register. The dBUG
initializes this register with the value 00 which provides for 1024 system clock time-out.
3.1.5 Interrupt Sources
The ColdFire family of processors can receive interrupts for seven levels of interrupt priorities. When the
processor receives an interrupt which has higher priority than the current interrupt mask (in status register),
it will perform an interrupt acknowledge cycle at the end of the current instruction cycle. This interrupt
acknowledge cycle indicates to the source of the interrupt that the request is being acknowledged and the
device should provide the proper vector number to indicate where the service routine for this interrupt level
is located. If the source of interrupt is not capable of providing a vector, its interrupt should be set up as
autovector interrupt which directs the processor to a predefined entry into the exception table (refer to the
MCF5204 User's Manual).
The processor goes to different service routine via the exception table. This table is in the Flash and the
VBR points to it. However, a copy of this table is made in the RAM starting at $00000000. To take over
an exception vector, the user places the address of the exception handler in the appropriate vector in the
vector table located at $00000000, and then points the VBR to $00000000.
The MCF5204 has four external interrupt request lines (-IRQ0, -IRQ1, -IRQ2, -IRQ3) and four internal
requests from Timer1, Timer2, Software watchdog timer, and UART. Each interrupt source , external and
internal, can be programmed for any priority level. In case of similar priority level, a second relative
priority between 1 to 3 will be assigned.
