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CHAPTER 3
HARDWARE DESCRIPTION AND RECONFIGURATION
This chapter provides a functional description of the SBC5204 board hardware. With the description given
here and the schematic diagram provided at the end of this manual, the user can gain a good understanding
of the board's design. In this manual, an active low signal is indicated by a "-" preceding the signal name.
3.1 THE PROCESSOR AND SUPPORT LOGIC
This part of the Chapter discusses the CPU and general supporting logic on the SBC5204 board.
3.1.1 The Processor
The microprocessor used in the SBC5204 is the highly integrated MCF5204, 32-bit processor. The
MCF5204 uses a ColdFire processor as the core with 512 bytes of instruction cache, a UART, two Timers,
512 bytes of SRAM, one-byte wide parallel I/O port, and the supporting integrated system logic. All the
registers of the core processor are 32 bits wide except for the Status Register (SR) which is 16 bits wide.
This processor communicates with external devices over a 16-bit wide data bus, D0-D15. This chip can
address the entire 4 G Bytes of memory space using internal chip-select logic. However, it provides only
22 address lines, A0-A21. All the processor's signals are available at J8 and J9 for off the board
expansion. Refer to section 3.7 for pin assignment.
The MCF5204 has an IEEE JTAG-compatible port and BDM port. These signals are available at J7 and
J9. The processor also has the logic to generate six (6) chip selects, -CS0 to -CS5.
3.1.2 The Reset Logic
The reset logic provides system initialization under two modes. Under system power-up and when the
RESET switch, S2 (red switch), is activated. The power-on and the RESET switch assert the processor's -
RESET line to reset the processor.
U4 is used to produce both active high and low RESET. The -RESET signal is for on board devices and
RESET is for the ISA Bus.
dBUG performs the following configurations of internal resources during the initialization. The instruction
cache is invalidated and disabled. The Vector Base Register, VBR, points to the Flash. However, a copy
of the exception table is made at address $00000000 in SRAM. To take over an exception vector, the user
places the address of the exception handler in the appropriate vector in the vector table located at
$00000000, and then points the VBR to $00000000.
The Software Watchdog Timer is disabled, Bus Monitor enabled, and internal timers are placed in a stop
condition. Interrupt controller registers initialized with unique interrupt level/priority pairs. The Port A
general purpose I/O pins are configured for dedicated peripheral functions, i.e. the UART.
