Programmer’s Model
3-6
Copyright © 2003, 2004. ARM Limited. All rights reserved.
ARM DDI 0306B
3.2
Register summary
All register addresses in the IPCM are fixed relative to the IPCM base address.
Table 3-1 summarizes the IPCM registers.
Table 3-1 IPCM register summary
Name
Base
offset
Type
Reset
value
Description
IPCM0SOURCE
0x000
RW
0x00000000
See
Mailbox Source Registers
on page 3-12
IPCM0DSET
0x004
WO
-
See
Mailbox Destination Set Registers
on page 3-12
IPCM0DCLEAR
0x008
WO
-
See
Mailbox Destination Clear Registers
on page 3-13
IPCM0DSTATUS
0x00C
RO
0x00000000
See
Mailbox Destination Status Registers
on
page 3-13
IPCM0MODE
0x010
RW
0x0
See
Mailbox Mode Registers
on page 3-13
IPCM0MSET
0x014
WO
-
See
Mailbox Mask Set Registers
on page 3-14
IPCM0MCLEAR
0x018
WO
-
See
Mailbox Mask Clear Registers
on page 3-15
IPCM0MSTATUS
0x01C
RO
0x00000000
See
Mailbox Mask Status Registers
on page 3-15
IPCM0SEND
0x020
RW
0x0
See
Mailbox Send Registers
on page 3-16
IPCM0DR0
0x024
RW
0x00000000
See
Mailbox Data Registers
on page 3-17
IPCM0DR1
0x028
RW
0x00000000
See
Mailbox Data Registers
on page 3-17
IPCM0DR2
0x02C
RW
0x00000000
See
Mailbox Data Registers
on page 3-17
IPCM0DR3
0x030
RW
0x00000000
See
Mailbox Data Registers
on page 3-17
IPCM0DR4
0x034
RW
0x00000000
See
Mailbox Data Registers
on page 3-17
IPCM0DR5
0x038
RW
0x00000000
See
Mailbox Data Registers
on page 3-17
IPCM0DR6
0x03C
RW
0x00000000
See
Mailbox Data Registers
on page 3-17
-
0x040-0x0
7C
-
-
Reserved for Mailbox1
-
0x080-0x0
BC
-
-
Reserved for Mailbox2
-
0x0C0-0x0
FC
-
-
Reserved for Mailbox3
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