Functional Overview
ARM DDI 0306B
Copyright © 2003, 2004. ARM Limited. All rights reserved.
2-21
Figure 2-8 Back-to-back messaging from Core0 to Core1
In this example, the following sequence occurs:
1.
Core0 gains control of Mailbox0 and identifies itself as the source core by setting
bit 0 in the IPCM0SOURCE Register.
2.
Core0 enables interrupts to Core0 and Core1 by setting bits 0 and 1 in the
IPCM0MSTATUS Register.
3.
Core0 defines the destination core by setting bit 1 in the IPCM0DSTATUS
Register.
4.
Core0 programs the data payload,
DA7A0000
.
5.
Core0 sets bit 0 of the IPCM0SEND Register to send the interrupt to the
destination core.
6.
Core1 reads the IPCMRIS1 Register and reads the data payload.
7.
Core1 optionally updates the data payload for the Acknowledge,
DA7A1111
.
8.
Core1 clears bit 0 and sets bit 1 in the IPCM0SEND Register to provide the
Manual Acknowledge back to Core0.
9.
Core0 reads the IPCMRIS0 Register and reads the data payload.
10.
Core0 programs the data payload for the next message,
DA7A2222
.
11.
Core0 clears bit 1 and sets bit 0 of the IPCM0SEND Register to send the interrupt
to the destination core.
IPCM0SOURCE[1:0]
IPCM0DSTATUS[1:0]
IPCM0MODE[1:0]
IPCM0MSTATUS[1:0]
IPCM0SEND[1:0]
IPCM0DR0[31:0]
IPCMRIS0[3:0]
IPCMRIS1[3:0]
IPCMINT[3:0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
0
0
00000000
0
0
0
0
0
3
1
0
0
2
1
2
1
2
1
2
1
0
1
0
DA7A0000
DA7A1111
00000000
2
0
DA7A2222
DA7A3333
1
0
1
0
1
0
0
0
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