Programmer’s Model
ARM DDI 0306B
Copyright © 2003, 2004. ARM Limited. All rights reserved.
3-3
Finally,
INTNUM
also defines which interrupt outputs are active. Although
IPCMINT[31:0]
is always 32 bits wide,
INTNUM
defines which bits can be set. For
example, when
INTNUM
is set to 1, only
IPCMINT[0]
can be set. When
INTNUM
is set to 32, all
IPCMINT[31:0]
bits can be set.
DATANUM
defines which IPCMxDATAn registers are available, where x is defined by
MBOXNUM
. Setting
DATANUM
to 0 means there are no IPCMxDATAn Registers
available. Setting
DATANUM
to 1 means the IPCMxDATA0 Registers are available.
Setting
DATANUM
to 7, means all IPCMxDATA0 to IPCMDATA6 Registers are
available.
Figure 3-1 on page 3-4 shows the IPCM register map.
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