Functional Overview
ARM DDI 0306B
Copyright © 2003, 2004. ARM Limited. All rights reserved.
2-23
Figure 2-10 Messaging from Core0 to Cores 1, 2, and 3 using Auto Acknowledge
In this example, the following sequence occurs:
1.
Core0 gains control of Mailbox0 and identifies itself as the source core by setting
bit 0 in the IPCM0SOURCE Register.
2.
Core0 sets Mailbox Mode Register bit 0 to put the mailbox into Auto
Acknowledge mode.
3.
Core0 enables interrupts to Core0, Core1, Core2, and Core3 by setting bits 0, 1,
2, and 3 in the IPCM0MSTATUS Register.
4.
Core0 defines the destination cores by setting bits 1, 2, and 3 in the
IPCM0DSTATUS Register.
5.
Core0 programs the data payload,
DA7A0000
.
6.
Core0 sets bit 0 of the IPCM0SEND Register to send the interrupts to the
destination cores.
7.
Core1 reads the IPCMRIS1 Register and reads the data payload.
8.
Core1 clears bit 1 in the IPCM0DSTATUS Register.
9.
Core3 reads the IPCMRIS3 Register and reads the data payload.
10.
Core3 clears bit 3 in the IPCM0DSTATUS Register.
IPCM0SOURCE[1:0]
IPCM0DSTATUS[1:0]
IPCM0MODE
IPCM0MSTATUS[3:0]
IPCM0SEND[1:0]
IPCM0DR0[31:0]
IPCMRIS0[3:0]
IPCMRIS1[3:0]
IPCMINT[3:0]
0
0
00000000
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
0
0
0
F
1
0
0
E
1
E
C
4
1
0
DA7A0000
00000000
15
2
0
1
0
1
0
IPCMRIS2[3:0]
0
1
0
IPCMRIS3[3:0]
0
1
0
C
4
0
1
0
0
16
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