Backplane Board
USA MAV500/MKVI Service Manual
12-12
28-00486-00
This document contains confidential information which is proprietary to ATI. It may not be disclosed to any unauthorized parties,
and it may not be copied. All rights reserved.
© Copyright (ATI) Aristocrat Technologies, Inc. 2002.
PIN
Pin Name, MAV/6
Main Board
Connects
to ...
Comment
C11
not used
-
Mechanical Security Switch 4 contact - NC
A12
not used
-
Emitter 6 Drive signal, security 6
B12
not used
-
Mechanical Security Switch 5 contact - NC
C12
not used
-
Receiver 5 Sense signal, security 5
A13
not used
-
Mechanical Security Switch 6 contact - NC
B13 GND
GND
Gnd
C13
not used
-
Receiver 6 Sense signal, security 6
A14
not used
-
Mechanical Security Switch 7 contact - NC
B14
not used
-
Receiver 7 Sense signal, security 7
C14
not used
-
Emitter 7 Drive signal, security 7
A15
IRQDMON
J2-A6
Demon Interrupt Line
B15 GND
GND
Gnd
C15 NC
-
-
A16
VBAT
J2-B4
Battery Backup Voltage
B16 NC
-
-
C16
not used
-
Spare IO
A17
not used
-
CPU, read not write signal
B17 GND
GND
Gnd
C17 NC
-
-
A18
NEIF
J3-C23
CPU, IF interrupt
B18
NEFHO
J3-C21
CPU, FH0 interrupt
C18
NDACK
J2-B5
CPU, data acknowledge
A19
NEFL
J3-C22
CPU, FL interrupt
B19 GND
GND
Gnd
C19
NEIL0
J2-A5
CPU, IL0 interrupt
A20
NERESET
J2-B7
CPU, external reset output
B20
NEIOW
J2-A7
CPU, IO write signal
C20
NEIOR
J2-B6
CPU, IO read signal
A21
not used
-
CPU, address bus 13
B21 GND
GND
Gnd
C21
ECLK8M
J2-A8
CPU, clock signal
A22
EA10
J2-B11
CPU, address bus
B22
EA11
J2-A11
CPU, address bus 11
C22
EA12
J2-B10
CPU, address bus 12
A23
EA8
J2-B12
CPU, address bus
B23 GND
GND
Gnd
C23
EA9
J2-A12
CPU, address bus
A24
EA5
J2-A14
CPU, address bus
B24
EA6
J2-B13
CPU, address bus
C24
EA7
J2-A13
CPU, address bus
A25
EA3
J2-A15
CPU, address bus
B25 GND
GND
Gnd
C25
EA4
J2-B14
CPU, address bus
A26 NC
-
-
B26 NC
-
-
C26
EA2
J2-B15
CPU, address bus
A27 NC
-
-
B27 GND
GND
Gnd
C27 NC
-
-
A28
ED5
J2-A19
CPU, data bus
B28
ED6
J2-B18
CPU, data bus
C28
ED7
J2-A18
CPU, data bus
A29
ED3
J2-A20
CPU, data bus
B29 GND
GND
Gnd