I/O Driver Board
USA MAV500/MKVI Service Manual
11-8
28-00486-00
This document contains confidential information which is proprietary to ATI. It may not be disclosed to any unauthorized parties,
and it may not be copied. All rights reserved.
© Copyright (ATI) Aristocrat Technologies, Inc. 2002.
11.2.1 Address Decoding
The I/O Driver Board includes address decoding which defines the address of each
I/O on the board. The I/O Driver does not manage all the I/O for the Main Board.
Refer to the chapter Main Board for a description of the I/O connected directly to the
Main Board. The following table lists the addresses of all I/Os on the I/O Driver
Board and the Main Board. The various signal names for MkV Main Board I/O have
been included as they are existing signals already used with previous MkV Main
Board designs.
Table 11-2 I/O Address Map
ADDRESS
READ / WRITE
BIT/S
NAME
SPARES
MAIN BD.
WRITE
NWRCS0 0x3010400
D7
DOPTOUT
NWRCS1 0x3010410
D0
CCINH
D2
HOPDIR
NWRCS5 0x3010450
D0
SOLDIV
D1
JPBELL
D2
HOPON
NWRCS4 0x3010440
D2
HOPTEST
I/O DRIVER
0x3012000
WRITE
D0..D7
PBL1..8
0x3012010
D0..D7
PBL9..14
4 + 2
0x3012020
D0..D5
HM1..6
2x
NC
0x3012030
D0..3
LTL1..4
D4..6
AL1..3
1x
NC
0x3012070
D0
LDSECO
D1
GDSHRIN
D2
BDSHRIN
D3
DDSHRIN
0x3012380
base address
PARALLEL
Port
DUART Channel 6,7
BACCLIT[1..8]
MAIN BD.
READ
NIOCS3 0x3010580
is
base address
ERROR
CCERROR
SELECT CCSEN
PE
CCRED
BUSY
SOLOPT
P3
AUSW
P4
JPSW
P5
BASW
P6
MECHSW
P7
CBOXSW
I/O DRIVER
0x3012000
READ
D0..7
PBS1..8
0x3012010
D0..7
PBS9..14
4 + 2 EXP
0x3012020
D0
GDSHRO
D1
BDSHRO
D2
DDSHRO
D4
HOPCOIN
D5
HOPHIGH
D6
DOPTIN
D7
LDSECIN
0x3012200
D0..D8
DIPSW1[1..8]
0x3012210
D0..D8
DIPSW2[1..8]