BIOS CONFIGURATION
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3.2.2.6 Max. Phy Link Rate
A SAS device is required to support all link rate between and
including the specified Max. and Min. hardware link rate. The
initiator determines the negotiated physical PHY link rate
along all pathways by querring all of the relevant PHYs during
discovery. If there is problem on the SAS speed negotiation
sequence, you can use this function to adjust the PHY link rate.
When you choose this option, the max PHY link rate on the same
expander or a different expander within the topology will set this
value.
Adapter#1- I/O=FD9FF000h, F2(Tab): Select Controller, F10: Reset System
ArrowKey Or AZ:Move Cursor, Enter: Select, ESC: Return To Previous Menu Item
Areca Technology Corporation SAS Controller
Main Menu
Physical Devices
Miscellaneous Settings
System Information
Miscellaneous Settings
Miscellaneous Settings
SATA NCQ Support
SMART Status Polling
Disk Write Cache
PCI Interrupt Type
PCIE Read Request Size
Max. Phy Link Rate
Max. Command Xfer Length
Delay Before Driver Load
INT 13 Service
Clear Persistent Mapping
Staggered Spin-up Config
Reset BIOS Parameters
PCIE Read Request Size
PCIE Read Request Size
128 Bytes
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
4096 Bytes
512 Bytes
3.2.2.5 PCIE Read Request Size
The PCI read request size parameter sets the maximum size of a
memory read request, which can be set to a maximum of 4096
bytes in 128-byte increments. The system uses the PCI read
request size to balance the allocation of bandwidth throughout
the topology. The maximum read request size also affects
performance because it determines how many read requests are
required to fetch the data.
Содержание ARC-1330 Series
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