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AWARD BIOS
3-11
Advanced Chipset Features
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SDRAM RAS Precharge Time
SDRAM RAS
Precharge Time
3
2
The RAS Precharge means the timing to inactive
RAS and the timing for DRAM to do precharge
before next RAS can be issued. RAS is the address
latch control signal of DRAM row address. The
default setting is
3 clocks
.
Advanced Chipset Features
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Video BIOS Cacheable
Video BIOS
Cacheable
Enabled
Disabled
Allows the video BIOS to be cached to allow faster
video performance.
Advanced Chipset Features
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Video RAM Cacheable
Video RAM
Cacheable
Enabled
Disabled
This item lets you cache Video RAM A000 and
B000.
Advanced Chipset Features
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Memory Hole At 15M-16M
Memory Hole At
15M-16M
Enabled
Disabled
This option lets you reserve system memory area
for special ISA cards. The chipset accesses
code/data of these areas from the ISA bus directly.
Normally, these areas are reserved for memory
mapped I/O card.
Advanced Chipset Features
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Delayed Transaction
Delayed Transaction
Enabled
Disabled
This item lets you control the Delayed Transaction
function of the PIIX4 chipset (Intel PCI to ISA
bridge). This function is used to meet latency of PCI
cycles to or from ISA bus. Try to enable or disable
it, if you have ISA card compatibility problem.
Advanced Chipset Features
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On-Chip Video