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Frequently Asked Questions
B-4
Q: When can we have real jumperless mainboard?
A: PnP had achieved the goal of jumperless add-on card, but true jumperless
mainboard still has some technical concerns. For example, CPU clock and
voltage do not have standard interface. Currently, the so called jumperless
mainboard is actually depends on the BIOS to detect or manually set the
CPU clock and voltage. If the setting is wrong, it will cause system unstable
or damage after long time use. The other disadvantage is, because some of
the jumper setting information is stored in CMOS, if the battery is lost or
BIOS setup is accidentally changed, end user (or distributor) may need to
open the housing and check the CPU again.
Most of all, you need a start voltage to boot CPU and go into BIOS for
jumperless setting. 2.85V may be OK for P55C and K6-166, but minimum
voltage of K6-233MHz is 3.1V, it can not boot if user plugs K6-233 onto
current jumperless mainboard.
We probably need to wait after the mature of SMbus, if CPU and clock
generator and other ICs are all SMbus compliance. Chipset can then detect
and report the system configuration right after power on. Then we can have
true jumperless mainboard.
Q: What is PBSRAM (Pipelined Burst SRAM)?
A: For Pentium CPU, the Burst means reading four QWord (Quad-word, 4x16 =
64 bits) continuously with only the first address decoded by SRAM. The
PBSRAM will automatically send the remaining three QWord to CPU
according to predefined sequence. The normal address decoding time for
SRAM is 2 to 3 clocks. This makes the CPU data read timing of four QWord
to be at least 3-2-2-2 and a total of 9 clocks if traditional asynchronous
SRAM is used. However, with PBSRAM, there is no need to decode address
for rest three Qword. Therefore, data read timing can be 3-1-1-1, that is
equivalent to 6 clocks and is faster than asynchronous SRAM.
Q: What is EDO (Extended Data Output) memory?
A: The EDO DRAM technology of EDO is actually very similar to FPM (Fast
Page Mode). Unlike traditional FPM that tri-states the memory output data
to start the pre-charge activity, EDO DRAM holds the memory data valid
until the next memory access cycle, that is similar to pipeline effect and
reduces one clock state.
Q: What is SDRAM (Synchronous DRAM)?
A: The SDRAM is a new generation DRAM technology that allows DRAM t o use
the same clock as the CPU host bus (EDO and FPM are asynchronous and
do not have clock signal). The idea is the same as "Burst" (refer to the
previous Q & A). It requires only one clock for the 2nd, 3rd, and 4th QWord