EVAL-ADAU1467Z
UG-1134
Rev. A (Draft) | Page 15 of 55
The signals pass through the
ADCs and then are sent
2
S format. The mapping
of input signals to input channels in
is shown in Table 1. See the
Error! Reference source not found.
section for the configuration of the
SDATAIOx pins.
Table 1. Mapping of Stereo Analog Input Signals to
Channels
Input Jack
Plug Contact
ADC Pins
Serial Input Pins
Input Channel in
J14
Left (tip)
ADC1LN, ADC1LP
SDATA_IN2
32
J14
Right (ring)
ADC1RN, ADC1RP
SDATA_IN2
33
J15
Left (tip)
ADC2LN, ADC2LP
SDATAIO4
36
J15
Right (ring)
ADC2RN, ADC2RP
SDATAIO4
37
Stereo Line Outputs
Four stereo output jacks allow eight line level analog output signals.
The
DAC outputs are configured such that a full-scale
signal is 2.8 V p-p at the jack, which is approximately 1 V rms
for a sine wave. The signals output from the DACs are fed to active
low-pass filters and then ac-coupled before reaching the output
jacks. The filters are designed for a system sample rate of 44.1 kHz
or 48 kHz.
The output filters are designed to drive high impedance loads,
for instance, loads at the input to active speakers. Some low
impedance loads (for example, loads from headphones) can also
be driven by these outputs. However, very low impedance loads
(for example, loads from passive speakers) cannot be driven by
these outputs.
The stereo output jacks accept standard stereo TRS 3.5 mm
(1/8 inch) mini plugs (tip connected to left, ring connected to
right, sleeve connected to ground) with two channels of audio
(see Figure 37).
The signals pass from the
serial outputs in I2S
DACs, where they are converted to
analog signals and sent through the output filters to the output
jacks. The mapping among the
output serial ports, and output jacks is shown in Table 2.
See the Configuring the SDATAIOx Pins for the ADCs and
DACs section for the configuration of the SDATAIOx pins.
Channels to Output Jacks
Output Jack
Plug Contact
DAC Pin
Serial Output Pin
Output Channel in
J12
Left (tip)
OL1
SDATA_OUT0
0
J12
Right (ring)
OR1
SDATA_OUT0
1
J13
Left (tip)
OL2
SDATAIO5
4
J13
Right (ring)
OR2
SDATAIO5
5
J18
Left (tip)
OL3
SDATAIO6
8
J18
Right (ring)
OR3
SDATAIO6
9
J17
Left (tip)
OL4
SDATAIO7
12
J17
Right (ring)
OR4
SDATAIO7
13
Configuring the SDATAIOx Pins for the ADCs and DACs
The EVAL-ADAU1467Z demonstrates how the SDATAIOx pins
make serial ports on the
input serial port and one output serial port is required to connect
the
codec using only stereo digital data
lines. The remaining serial ports are available to connect to
other audio inputs and outputs.
The SDATAIOx pins provide additional serial audio data inputs
or outputs and expand the functionality and versatility of the
serial ports. In earlier generations of the
architecture,
serial ports are limited to a single SDATA pin. If this serial data
pin is configured in a stereo mode, the remaining channels
associated with the port are inaccessible. Device interfaces with
a single LRCLK and BCLK pair and multiple stereo data lines
(for example, in a case with multiple connections in the I
2
S
format) required using multiple
serial ports.
The SDATAIOx pins on the
eliminate this bottleneck.
The connection between the
codec
uses four I
2
S data lines for the eight DAC channels and two I
2
S
data lines for the four ADC channels. The
EVAL-ADAU1467Z supplements the SDATA_OUT0 pin
with three SDATAIOx pins and the SDATA_IN2 pin with one
SDATAIOx pin. This configuration connects all of the audio
channels of the
while using only one input serial port
and one output serial port. The connections are shown in
Figure 38.
Содержание SigmaDSP ADAU1463
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Страница 48: ...UG 1134 EVAL ADAU1467Z Rev A Draft Page 48 of 55 Figure 114 EVAL ADAU1467Z Layout Layer 5 Ground D R A F T...
Страница 49: ...EVAL ADAU1467Z UG 1134 Rev A Draft Page 49 of 55 Figure 115 EVAL ADAU1467Z Layout Bottom Copper D R A F T...