ADSP-21375 EZ-KIT Lite Evaluation System Manual
2-3
ADSP-21375 EZ-KIT Lite Hardware Reference
The
CLKIN
pin of the processor connects to a 16.384 MHz oscillator. The
core frequency of the processor is derived by multiplying the frequency at
the
CLKIN
pin by a value determined by the state of the processor pins
CLKCFG1
and
CLKCFG0
. The value at these pins is determined by the state of
the
SW2
switch (see
“Boot Mode and Clock Ratio Select Switch (SW2)” on
). By default, the EZ-KIT Lite gives a core frequency of
262.144 MHz. It is possible to change the speed of the processor by
changing the value of the
PMCTL
register.
The
SW2
switch also configures the boot mode of the processor. The
EZ-KIT Lite is capable of EPROM/flash boot and SPI boot. By default,
the EZ-KIT Lite boots from the flash memory. For information about
configuring the boot modes, see
“Boot Mode and Clock Ratio Select
External Port
The external port of the ADSP-21375 processor consists of a 24-bit
address bus, 16-bit data memory bus, and control lines. The control lines
are used to select, read, and write to external memory devices.
The external port connects to an 8-bit parallel flash memory and a 16-bit
SDRAM memory. See
for more informa-
tion about accessing the flash and SDRAM memories.
All of the external port signals are available externally via the expansion
interface connectors (
J1–3
). The pinout of the connectors can be found in
“ADSP-21375 EZ-KIT Lite Schematic” on page B-1
.
