Analog Devices EVAL-ADIN1300, Руководство пользователя

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EVAL-ADIN1300FMCZ User Guide UG-1635
Rev. 0 | Page 5 of 30
The ADIN1300 can also be configured to provide a 25 MHz clock
output on the CLK25_REF pin, which is available on the FMC
connector. The source of this clock is the on-board Y1 crystal. Note
that when a pin reset is applied to the
ADIN1300 , the clock
disappears for the duration of the reset and must be reenabled
via the Ethernet PHY software following the reset. This clock can
be used to synchronously clock the FPGA logic. If a reset for
ADIN1300 is required without CLK25_REF stopping, use a
software reset instead. Alternatively, the GP_CLK pin is also
available on the FMC connector and can be configured to output
several different clocks from the
ADIN1300 . See the ADIN1300
data sheet for more information.
ON-BOARD EEPROM AND LEDS
The EVAL-ADIN1300FMCZ has two FPGA controllable LEDs
and one unprogrammed, I
2
C EEPROM, U7.
U7 can be programmed with voltage settings to allow the FPGA
board to provide the correct voltages on the supply rails. The
write address of the EEPROM is 0b[10100 [GA1] [GA0] 0] and
the read address is 0b[10100 [GA1] [GA0] 1].
ADIN1300 LED PIN
There is one LED pin (LED_0) on the ADIN1300 . The LED_0 pin
can be configured in various operating modes using the MDIO
interface dongle (see the
ADIN1300 data sheet). By default, the
LED_0 pin LED illuminates when a link is established, and
flashes when there is activity.
The LED_0 pin is a multifunction pin shared with the
PHY_CFG0 pin configuration function. Therefore, it can be
necessary for the voltage level on the LED_0 pin to be set at a
certain value at power-on and reset to configure the
ADIN1300
as required. See the ADIN1300 data sheet for more information
on the multilevel strapping being used as part of the hardware
configuration.
The LED_0 pin has a two-pole rotary switch, S1, to allow easy
configuration for all modes of the PHY_CFG0 pin (as set by S4).
Table 4 describes how S1 should be configured for the appropriate
S4 PHY_CFG0 pin setting. The LED_0 pin is driven from the
AVDD3P3 supply rail, see Figure 2.
Table 4. S1 Switch Positions
Jumper S4, PHY_CFG0 S1 Position
JP1 Mode 3 and Mode 4 1
JP2 Mode 1 and Mode 2 2
MODE 3 AND MODE 4
MODE 1 AND MODE 2
R192
100k Ω
R110
0 Ω
AVDD3P3
BC817
Q2
1
2
3
S1
LED_0
A
C
DS1
2
3
1
R193
10 Ω
R191
0 Ω
R43
390 Ω
214
19-
003
Figure 2. Hardware LED_0 Pin Configuration
MDIO INTERFACE
The MDIO interface of the ADIN1300 can be accessed directly
through the P5 connector to connect the MDIO interface
dongle to the PHY.
The MDIO interface dongle also allows interfacing with the
EVAL-ADIN1300FMCZ via the Ethernet PHY software graphical
user interface (GUI) running on the PC (see Figure 3).
ADIN1300
25MHz
CRYSTAL
POWER
FMC
CO
NNE
CT
O
R
P3
MDIO
P5
MAGNETICS
RJ45
CONNECTOR
EVAL-ADIN1300FMCZ
OPTIONAL
MDIO INTERFACE
DONGLE
BOOT
STRAP
RESISTOR
MODE
SELECT
LED0
P7
ADuCM3029
FTDI
UART TO USB
USB
EXTERNAL
CLOCK
214
19-
004
Figure 3. Simplified Overview of EVAL-ADIN1300FMCZ with MDIO Interface
Dongle Connected