UG-1635
Rev. 0 | Page 18 of 30
LAYOUT GUIDELINES
BOARD STACKUP
The EVAL-ADIN1300FMCZ consists of a 4-layer PCB: the top
layer, Layer 2, Layer 3, and the bottom layer. All layers have a
copper pour, with an exception around sensitive traces for the
MAC and MDI interfaces.
GROUND PLANES
The top and bottom layers of the EVAL-ADIN1300FMCZ
mainly carry signal and routing signals from the
The two inner layers are used for ground planes. Layer 2 is a full
ground plane. Layer 3 contains primarily of ground with area
dedicated to the DVDD and VDDIO power planes. Although
the
is a mixed signal device, it only has one type of
ground return, GND.
ISOLATION GUIDELINES
Transformer Layout
No metal layers can be directly underneath the transformer to
minimize any noise coupling across the transformer.
RJ45 Layout
For optimal electromagnetic computability (EMC) performance,
use a metal shielded RJ45 connector with the shield connected to
chassis ground. There must be an isolation gap between the chassis
ground and the IC GND with consistent isolation across all layers.
POWER SUPPLY DECOUPLING
From a PCB layout point of view, it is important to locate the
decoupling capacitors as close as possible to the power supply
and GND pins to minimize the inductance.
MAC INTERFACE
When routing the MAC interface traces, ensure that the lengths
of the pairs are matched. Avoid crossover of the signals where
possible. Stubs should be avoided on all signal traces. It is
recommended to route traces on the same layer.
MANAGEMENT INTERFACE
MDI interface
Traces running from the MDI_[x]_P/N pins of the
to the magnetics must be on the same side of the EVAL-
ADIN1300FMCZ (no vias), kept as short as possible (less than
1 inch in length), and individual trace impedance of these
tracks must be kept below 50 Ω with a differential impedance of
100 Ω for each pair. The same recommendations apply for
traces running from the magnetics to the RJ45 connector.
Impedance must be kept constant throughout. Any
discontinuities can impact signal integrity.
Each pair must be routed together with trace widths the same
throughout. Trace lengths must be kept equal where possible
and any right angles on these traces must be avoided (use curves or
45° angles in the traces). Stubs must be avoided on all signal
traces. It is recommended to route traces on the same layer.
PLACEMENT OF THE TVS DIODE
It is recommended to place the TVS diode close to the
device to ensure minimal track inductance between the external
protection and internal protection within the device.
THERMAL CONSIDERATIONS
is packaged in an LFCSP package. This package
is designed with an exposed paddle which must be soldered to
the PCB for mechanical and thermal reasons. The exposed
paddle acts to conduct heat away from the package and into the
PCB. By incorporating an array of thermal vias in the PCB thermal
paddle, heat is dissipated more effectively into the inner metal
layers of the PCB. When designing the PCB layout for optimum
thermal performance, use a 4 mm × 4 mm array of vias under
the paddle.
This LFCSP device includes two exposed power bars adjacent to
the exposed pad at the top and bottom, highlighted in red in
Figure 36. These bars are connected to internal power rails and
the area around them is a keep out zone. Keep these areas clear
of traces or vias.
1
0.50
BSC
BOTTOM VIEW
40
11
20
21
30
31
10
0.025 REF
0.15
REF
0.30
0.25
0.20
0.24
0.14
0.04
0.475
0.375
0.275
0.785
0.685
0.585
2.87
2.77
2.67
0.50
0.40
0.30
2.90
2.80 SQ
2.70
EXPOSED
PAD
PIN 1
214
19
-037
Figure 36. LFCSP Simplified Package Drawing with Keep Out Area for Power
Bars Highlighted (Underside)
