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EVAL-ADIN1200FMCZ

User Guide

UG-1673

Rev. 0 | Page 7 of 29

Table 5. EVAL-ADIN1200FMCZ Configuration Settings

Configuration Options

Relevant Pins

Resistor and Switch Settings

PHY Address = 0b00000

RXD_3/PHYAD_3

R22, R29, R31, R37 = do not install

RXD_2/PHYAD_2

R23,

R30,

R32, R38 = do not install

RXD_1/PHYAD_1

Using internal pull-down resistors

RXD_0/PHYAD_0

MDIX Mode Configuration

GP_CLK/RX_ER/MDIX_MODE

S9 Position 1, Mode 1, manual MDI

S9 Position 2, Mode 2, manual MDIX

S9 Position 3, Mode 3, prefer MDIX

S9 Position 4, Mode 4, prefer MDI (default)

PHY Configuration

LINK_ST/PHY_CFG1

Controlled by S1, S3, and S4 switches to provide the various
configuration options (see the

ADIN1200

data sheet)

Downspeed, EDPD, Energy

Efficient Ethernet (EEE),
Software Power-Down,
Forced Speed

LED_0/COL/TX_ER/PHY_CFG0

Default

configuration:

S3 = 1 or 2 for the PHY_CFG1 function, note that the EVAL-
ADIN1200FMCZ boards are shipped in pairs with one board
set to 1 and the other set to 2

S4 = 4 for the PHY_CFG0 function, and S1 = 1 for the LED_0
function

MAC Interface Selection

RX_CTL/RX_DV/CRS_DV/MACIF_SEL1

R8, R9 = do not install

RXC/RX_CLK/MACIF_SEL0

R27, R28 = do not install

Using internal pull-down resistors results in MAC interface
default selection being the reduced gigabit media
independent interface (RGMII) MAC interface with 2 ns internal
delay on the RXC signal and TXC signal

Figure 7. Configuration Resistor Placement, Underside of PCB

Содержание EVAL-ADIN1200

Страница 1: ...vailable to download on the ADIN1200 product page DOCUMENTS NEEDED ADIN1200 data sheet GENERAL DESCRIPTION The EVAL ADIN1200FMCZ allows simplified evaluation of the key features of the ADIN1200 robust industrial low power 10 Mbps and 100 Mbps Ethernet physical layer PHY The EVAL ADIN1200FMCZ is powered by a single external 5 V supply rail that can be supplied either via the EXT_5V connector or via...

Страница 2: ...e Evaluation Software 10 Board Display Showing Connected EVAL ADIN1200FMCZ Hardware 11 User Buttons Section 11 Link Properties Tab 11 Register Access Tab 12 Clock Pin Control Tab 13 Loopback Tab 13 Test Modes Tab 13 FrameGenerator Checker 13 Cable Diagnostics Tab 14 Activity Information Window and Linking Status 15 Activity Log Information Section 15 Loading a Script File 15 Troubleshooting 17 Sof...

Страница 3: ...EVAL ADIN1200FMCZ User Guide UG 1673 Rev 0 Page 3 of 29 EVAL ADIN1200FMCZ WITH OPTIONAL MDIO INTERFACE DONGLE CONNECTED 22009 001 Figure 1 ...

Страница 4: ...e ADIN1200 in IEEE 802 3 test modes establish links with a link partner and evaluate the performance of the chip In standalone mode power the EVAL ADIN1200FMCZ with a 5 V supply at the EXT_5V connector Alternatively the EVAL ADIN1200FMCZ has an FMC low pin count LPC connector that can be plugged into an FPGA development board When used with an FPGA board the media independent interfaces MIIs clock...

Страница 5: ...e 3 and Mode 4 1 JP2 Mode 1 and Mode 2 2 MODE 3 AND MODE 4 MODE 1 AND MODE 2 R192 100kΩ R110 0Ω AVDD3P3 BC817 Q2 1 2 3 S1 LED_0 A C DS1 2 3 1 R193 10Ω R191 0Ω R43 390Ω 22009 002 Figure 2 Hardware LED_0 Pin Configuration MDIO INTERFACE The MDIO interface dongle can be accessed directly through the P5 connector to connect the MDIO interface to the PHY The MDIO interface dongle also allows interfacin...

Страница 6: ...esets the on board ADuCM3029 BOTTOM TOP S5 S6 USB ADuCM3029 22009 005 Figure 5 Overview of MDIO Interface Dongle CONFIGURATION PINS SETUP The EVAL ADIN1200FMCZ default configuration and configuration options are detailed in Table 5 The ADIN1200 configuration settings can be changed by manipulating the resistors listed in the right column See the ADIN1200 data sheet for more details on all availabl...

Страница 7: ...o provide the various configuration options see the ADIN1200 data sheet Downspeed EDPD Energy Efficient Ethernet EEE Software Power Down Forced Speed LED_0 COL TX_ER PHY_CFG0 Default configuration S3 1 or 2 for the PHY_CFG1 function note that the EVAL ADIN1200FMCZ boards are shipped in pairs with one board set to 1 and the other set to 2 S4 4 for the PHY_CFG0 function and S1 1 for the LED_0 functi...

Страница 8: ...The MDIO interface dongle uses the FT232RQ for UART to USB communication The MDIO interface dongle requires the installation of drivers for the FTDI Chip USB UART IC Locate and install this driver separately These drivers are available at the FTDI website Ethernet PHY Software GUI Installation To install the Ethernet PHY software GUI take the following steps 1 Launch the installer file to begin th...

Страница 9: ...MODEL_NUM to determine what device is connected and configure the software GUI accordingly ADIN1200 or ADIN1300 INITIAL SETUP To set up the EVAL ADIN1200FMCZ and use it with the Ethernet PHY software GUI take the following steps 1 Connect a 5 V power supply to the EVAL ADIN1200FMCZ via the EXT_5V connector or the 5 V barrel connector 2 Connect the USB cable to the MDIO interface dongle 3 Connect t...

Страница 10: ...ice registers 5 Clock Pin Control tab Controls which clock is applied to the GP_CLK RX_ER MDIX_MODE pin 6 Loopback tab Controls the various loopback modes 7 Test Modes tab Provides access to the various test modes on the device 8 FrameGenerator Checker tab Configures and enables the frame generator and frame checker 9 Cable Diagnostics tab Provides easy access to the cable diagnostics features on ...

Страница 11: ...are grey and disabled Disable or Enable Linking Click Disable Linking to disable linking when a link is up The button changes from Disable Linking to Enable Linking Click Enable Linking to enable linking Restart Linking If the software configuration has been changed click Restart Linking to restart the linking process with the new config uration If the link is already established the link is first...

Страница 12: ...number of attempts to bring up a link at the highest advertised speed Downspeed Retries sets the number of times the PHY attempts to bring up a link The default is four attempts MDIX use the dropdown menu to choose Auto MDIX FixedMDI or FixedMDIX FixedMDI and FixedMDIX not shown in Figure 18 Energy Detect PowerDown Mode use the dropdown menu to choose Disabled Enabled or EnabledWithPeriodicPulseTx...

Страница 13: ...functions in the device Select the appropriate test mode and click Execute Test see Figure 24 22009 024 Figure 24 Test Modes Tab FRAMEGENERATOR CHECKER This tab provides access to the frame generator and frame checker features of the ADIN1200 see Figure 25 Control the number of frames generated by the generator the frame length and the content of the frame within this tab Choose to have the frame ...

Страница 14: ...e measurements are displayed in the main Link Properties tab The features in the Cable Diagnostics tab see Figure 27 are available to run when the link is disabled such as checking for short circuits checking for open circuits and identifying the distance to the first fault see Figure 29 The LINK_EN bit must be clear to run these checks 22009 027 Figure 27 Cable Diagnostics Configuration with Link...

Страница 15: ...al PHY which indicates the various reads writes and information on whether a link is established When the frame generator is enabled this window shows the frame generator activity The board identification is recorded with each bit field change to clarify which device is being addressed 22009 033 Figure 33 Activity Log Showing Device Status To clear the activity log right click and then click Clear...

Страница 16: ...lly Create the sequence of write commands using a text editor Ensure that the exact syntax is copied and match the register names with those in the data sheet to prevent errors reported in the activity log Give the script a unique name When the SftPd Down Up routine is selected see the following example Name SftPd Down Up RegisterAccesses MemoryMap GEPhy RegisterName SftPd Value 1 MemoryMap GEPhy ...

Страница 17: ...r to the MDIO interface dongle the GUI may not properly establish communications with the MDIO interface dongle The GUI polls for the MDIO interface dongle regularly and if an error in the MDIO interface dongle communications is found it is flagged in the Activity Log section and highlighted in red font as shown in Figure 36 The message also includes a prompt explaining how to resolve the issue In...

Страница 18: ...I Interface Traces running from the MDI_x_P or MDI_x_N pins of the ADIN1200 to the magnetics must be on the same side of the EVAL ADIN1200FMCZ no vias kept as short as possible less than 1 inch in length and individual trace impedance of these tracks must be kept below 50 Ω with a differential impedance of 100 Ω for each pair The same recommendations apply for traces running from the magnetics to ...

Страница 19: ... C11 C12 R53 LINK_ST R192 R34 R104 R193 DS1 R43 Q2 S4 R196 R103 R117 22009 037 R116 R118 R209 R207 R194 S9 R206 R197 R208 R195 GND1 J1 R145 S2 R114 R115 R51 R39 S3 C63 R120 R107 R106 C38 C36 C37 C34 C10 C41 R19 C42 Y1 R24 R40 R33 R37 R38 R31 R32 R29 R30 R23 R22 D3 VDDIO XTAL_O MDI_1_P XTAL_O RSTN AVDD3P3 RESET VDDIO MODE4 MODE3 MODE2 MODE1 PHY_CFG0_MODE1 PHY_CFG0_MODE2 PHY_CFG0_MODE3 PHY_CFG0_MODE...

Страница 20: ...re 38 Magnetics PLACEHOLDERS FOR ADDITIONAL DECOUPLING ADP223 MAX VIN 5 5V ALONG THE SUPPLY TRACE ADP223 PLACE VIN AND VOUT CAPACITORS AS CLOSE AS POSSIBLE TO THE PINS INSERTED RESISTOR FOOTPRINT CAN BE USED FOR CURRENT MEASUREMENTS INSERTED CHANGE R16 TO 280K FOR VDDIO 3 3V CHANGE R16 TO 130K FOR VDDIO 1 8V VDDIO DEFAULT IS 2 5V MAX INPUT VOLTAGE 5 5V VOUT1 AVDD3P3 0 5 1 280K 50K VOUT2 VDDIO 2 5V...

Страница 21: ...LINK_ST GP_CLK RX_ER LED_0 LED_A LED_B GA0 SCL 3P3_FPGA TXCTL MDIO MDC MDC_FMC MDIO_FMC RESET VDDIO 3P3 AUX 3P3 AUX GA1 SCL TXD3 RX_CTL RX_DV TXD1 RXD_1 RX_CTL RX_DV RXC RX_CLK RXD_1 RXD_0 TX_CTL TX_EN TXC TX_CLK TXD_3 TXD_2 TXD_1 SW_1 TXD0 RXD_2 RXCTL RXDV MDC_FMC MDIO_FMC TXD_2 RXD1 RESET LED_0 INT_N CRS SW_4 CON CRS IO_SCL SW_6 SW_5 IO_SDA LED_A TXD_0 VIO RXD_0 LED_0 RXD_2 RXD_3 TXD_0 RXD2 CON ...

Страница 22: ...1 1 4 5 3 2 1 1 19 14 15 30 26 2 32 3 18 28 27 29 25 23 13 12 5 20 17 4 PAD 31 6 7 8 9 11 10 21 22 24 16 5 4 3 2 1 G2 G1 3 2 1 8 7 6 4 PAD 5 AC 3 1 42 1 2 4 3 2 1 4 3 2 1 1 1 1 1 1 52 51 47 50 13 12 9 11 10 7 6 49 34 8 1 14 58 57 41 46 5 4 25 3 2 36 35 45 37 55 54 53 56 31 30 33 29 32 44 62 61 59 60 63 PAD 24 26 43 42 38 27 28 15 48 64 39 40 23 22 21 20 19 18 17 16 A C B VCC A GND Y VCC VCCIO CBUS...

Страница 23: ...EVAL ADIN1200FMCZ User Guide UG 1673 Rev 0 Page 23 of 29 22009 042 Figure 42 Schematic Silkscreen Top 22009 043 Figure 43 Schematic Silkscreen Bottom ...

Страница 24: ...UG 1673 EVAL ADIN1200FMCZ User Guide Rev 0 Page 24 of 29 22009 044 Figure 44 Top Layer 22009 145 Figure 45 Layer 2 Ground Layer ...

Страница 25: ...EVAL ADIN1200FMCZ User Guide UG 1673 Rev 0 Page 25 of 29 22009 045 Figure 46 Layer 3 Power and Ground Layer 22009 046 Figure 47 Layer 4 Bottom Layer ...

Страница 26: ...ration 2 C75 C82 Capacitor 20 pF 16 V 5 C0402 C0G 0402YA200JAT2A AVX Corporation 2 C83 C84 Capacitor 0 47 μF 35 V 10 C0603 X7R GMK107B7474KAHT TAIYO YUDEN 2 C86 C88 Capacitor 2 2 μF 50V 10 C0805 X7R UMK212BB7225KG T TAIYO YUDEN 1 D3 6 V SOT23_6 TVS array low capacitance electrostatic discharge ESD protection SP0504SHTG Littelfuse Inc 3 DS1 DS4 DS5 1 7 V LED red clear 660 nm SML LX0805SRC TR Lumex ...

Страница 27: ...1000C Panasonic 1 R149 Resistor 82 kΩ 1 R0603 MC 0 063W 0603 1 82K Multicomp SPC 1 R16 Resistor 200 kΩ 1 R0603 ERJ 3EKF2003V Panasonic 1 R192 Resistor 100 kΩ 1 R0603 RC0603JR 07100KL Yageo 1 R193 Resistor 10 kΩ 1 R0402 ERJ 2RKF1002X Panasonic 4 R2 to R5 Resistor 75 Ω 1 R0603 ERJ 3EKF75R0V Panasonic 1 R43 Resistor 390 Ω 5 R0402 ERJ 2GEJ391X Panasonic 2 R7 R46 Resistor 470 Ω 1 R0402 RC0402FR 07470RL...

Страница 28: ...er 15 12V_FPGA GND1 GND3 GND5 GPCLK INT_N LDO_CAP LED_0 LINK_ST MDC MDIO P9 P10 P11 SUPPLY Test point do not insert 1405 2 Keystone Electronics 5 C5 C6 C18 C55 C92 Capacitor 0 1 μF 16 V 10 C0402 X7R 530L104KT16T American Technical Ceramics 4 C33 C45 C91 C99 Capacitor 0 01 µF 25 V 10 0402 X7R TDK C1005X7R1E103K050EB 1 J1 PCB connector straight SubMiniature Version A SMA TE Connectivity LTD 5 181483...

Страница 29: ...ose or transfer any portion of the Evaluation Board to any other party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred damages or ...

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