System Architecture
2-2
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
board.
This EZ-KIT Lite has been designed to demonstrate the capabilities of the
ADSP-TS201S TigerSHARC processor. The processor is powered by
three separate regulators for the core, internal DRAM, and IO. The pro-
Figure 2-1. System Architecture
CPLD
JTAG
Header
Power Regulation
External Bus
Interface Unit
Analog Devices
Type A
EZ-Kit Expansion
Interface
+7.5V
C
onnector
Link Port 0
SDRAM 32MB
(2chips x 4M x 32bits)
PBs
Link Port
Connectors
4 - RJ45
(2 per port)
AD1854
DAC
AD1871
ADC
ADSP-TS201
Link Port 1
Link Port 2
Link Port 3
JTAG Port
FLAGs
IRQs
Clock Mult
(Default 5x)
LEDs
Flash
(512K x 8 bits)
External Bus
Interface Unit
Link Port 0
ADSP-TS201
Link Port 1
Link Port 2
Link Port 3
JTAG Port
FLAGs
IRQs
VDD_CORE
VDD_DRAM
PLL
1.5V
VDD_IO
1.05V
2.5V
3.3V
5V
Stereo
Jack
Stereo
Jack
EBIU
1.05V
1.5V
2.5V
PLL
20MHz
Osc
100MHz SCLKin
CPLD I/O
Header
Содержание ADSP-TS201S EZ-KIT Lite
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