Analog Devices ADSP-CM403F EZ-KIT Lite, Руководство пользователя

Страница: 73 / 75

ADSP-CM403F EZ-KIT Lite Evaluation System Manual I-1
I INDEX
A
ADSP-CM403F processor, x
analog connector (J9), 2-21
architecture, of this EZ-KIT Lite, 2-2
asynch or memory connector (J2), 2-20
B
bill of materials, A-1
board schematic (ADSP-CM403F), B-1
bus switch, 2-5
example, 2-6
C
CAN0 connector (J8), 2-21
character display connector (J3), 2-20
configuration, of this EZ-KIT Lite, 1-3
connectors, 2-19
diagram of locations, 2-19
J1 (DCE UART), 2-20
J2 (asynch or memory), 2-20
J3 (character display), 2-20
J7 (PWM), 2-21
J8 (CAN0), 2-21
J9 (analog), 2-21
P1 (JTAG/SWD/SWV), 2-21
P2 (TRACE and JTAG/SWD/SWV),
2-22
P3 (VREF buffered), 2-22
P7 (power), 2-22
contents, of this EZ-KIT Lite package, 1-2
D
DCE UART connector (J1), 2-20
debug interface, 1-10
default configuration, of this EZ-KIT Lite,
1-3
default jumper and switch settings, 1-4
default processor interface availability, 2-7
design reference information, 1-13
E
EngineerZone, xviii
example programs, 1-13
expansion interface, 1-11
F
FET switches, 2-4
example, 2-4
G
general-purpose I/O pins (GPIO), 2-18
I
installation, of this EZ-KIT Lite, 1-4 , 1-5
J
JTAG/SWD/SWV connector (P1), 2-21
jumpers
diagram of locations, 2-14