System Architecture
2-2
ADSP-CM403F EZ-KIT Lite Evaluation System Manual
System Architecture
This section describes the processor’s configuration on the EZ-KIT Lite
(
This EZ-KIT Lite is designed to demonstrate the ADSP-CM403F proces-
sor’s capabilities. The ADSP-CM403F EZ-KIT Lite has a 30 MHz input
clock and runs at 240 MHZ internally.
Figure 2-1. EZ-KIT Lite Block Diagram
ADSP-CM403F
LEDs (3)
D
e
bug
Po
rt
SPI0
30 MHz
Oscillator
3.3 Volts
PBs (2)
RS-232
ADM3252E
CL
KIN
GPIO
Analog Connector
120 pin 0.5mm connector
AGND, 5V out, GND
32 Mbit Quad
SPI Flash
AFE
2 16-bit ADCs
12 inputs each
2 12-bit
DACs
PWM Connector
180 pin 0.5mm connector
5V in, 5V out, 3.3V out, GND
UART0
CAN0
RJ11
DB9
Female
ADI
ADM3053
JTAG
20 pin 0.1"
TRACE
20 pin 0.05"
PWM0:2
SINC0
CNT0:1
TWI0
LCD
display
2x20
SMC0
Asynchronous
connector
180 pin 0.5mm connector
5V/3.3V out, GND
UART2
TMR0:2
SPI2