ADSP-BF526 EZ-Board Evaluation System Manual
1-35
Using The ADSP-BF526 EZ-Board
Power Saving Features
The ADSP-BF526 EZ-Board is designed for low-power application evalu-
ations; use the following settings to enable the board’s power saving
features.
• Jumper-controlled power savings
• The Ethernet PHY (SMSC LAN8700) can be totally pow-
ered down by removing jumpers
P21
and
P22
.
• The UART line drivers can be powered down by placing a
jumper on
JP14
and then removing any jumper from
JP3
.
• The reset and Ethernet LED voltage translator can be dis-
abled by removing any jumper from
JP11
.
• The GPIO LED’s and OTP flag voltage translator can be
disabled by removing any jumper from
JP5
.
• Processor-controlled power savings
The VDDINT regulator (
VR5
) can be shut down with the
EXT_WAKE
signal of the processor.
EXT_WAKE
also controls:
• The OTP flag and LED voltage translator (
U3
) via
JP5
• The Ethernet LED and reset voltage translator (
U4
) via
JP11
• The UART1 voltage translator (
U32
) via
JP3
Refer to the
ADSP-BF52x Blackfin Processor Hardware Reference
for
more information about
EXT_WAKE
; refer to
for more information about the jumpers.
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