ADMV8913-EVALZ
Evaluation Board User Guide
UG-1952
Rev. 0 | Page 11 of 17
PLUG-IN SPI REGISTER CONTROLLER
The
ADMV8913
plug-in utilizes an SPI register controller to
communicate with the ADMV8913. When using the ADMV8913
in a system, it is recommended to follow a similar methodology
for implementing SPI communication. The following is a
summary of the SPI register controller:
1.
Determine if Register 0x000 is not set to 0x3C.
2.
If Step 1 is true, set Register 0x000 to 0x3C to enable the
SDO pin on the ADMV8913 and allow SPI streaming with
Endian register ascending order.
3.
Determine if the values have changed for any of the LUT
registers (Register 0x100 to Register 0x17F).
4.
If Step 3 is true, write Register 0x100 to Register 0x17F by
performing the following:
•
Pointing to Register 0x100 and streaming out 64 bytes
of data
•
Pointing to Register 0x140 and streaming out 64 bytes
of data
5.
If Step 4 has occurred, write dummy data to Address 0x0A.
Note that Address 0x0A does not exist in the ADMV8913,
and the written dummy data is ignored. This step is
microcontroller architecture dependent and can be ignored
in most cases. It is necessary for the
SDP-S
to clear the SPI
bus and reconfigure for a standard 24-bit SPI transaction.
6.
Write out any remaining registers that may have changed.
7.
Determine if the values have changed for any of the SFL
registers, Register 0x011 to Register 0x013.
8.
If Step 7 is true, read back the FAST_LATCH_STATE from
Register 0x014.
PARALLEL MODE
The ADMV8913-EVALZ can be configured to operate the
ADMV8913 chip in parallel mode. Slide the S2 switch up
for parallel mode. Parallel mode allows the filter to be
programmed without software by supplying logic states to
the parallel logic input pins (HPF_B3 to HPF_B0 and LPF_B3
to LPF_B0) using the P3 connector.
For synchronous parallel mode operation, the filter state does
not change until the CS pin is brought high by pressing the
CSB
Toggle S4
button. For asynchronous operation, tie the CS pin
high using Pin 18 of P3 because this allows the filter state to update
immediately upon any change to the parallel logic input pins.
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