Analog Devices AD9874, Руководство пользователя

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REV. 0
EVAL-AD9874EB
–8–
R21
50
⍀
A B
1
2
3
JP23
VDDA
VDDF
TP21
PC
PD
TP22
C98
VAL C32
VAL C34
VAL
R51
VAL C83
0.1
␮
F
CLKN
CLKP
VDDC
IOUTC
VDDQ
VDDD
VDDH
FREF
IOUTL
VDDP
VDDL
LON
LOP
VDDI
SYNCB
FS
DOUTB
DOUTA
11
12
14
6
17
9
13
24
23
1
2
15
5
4
21
16
3
22
18
10
7
8
19
20
39
40
48
27
26
33
25
43
42
38
47
34
37
36
45
32
31
35
30
29
41
44
46
28
CLKOUT
U1
DUT-AD9874
CLKN
CLKP
GCN
GCP
GNDA
GNDC
GNDD
GNDF
GNDQ
GNDS
IF2N
IF2P
IOUTC
MXON
MXOP
PC
PD
RREF
VDDA-ADC
VDDC_CK_SYNTH
VDDF
VDDQ_CK_PUMP
VREFN
VREFP
CLKOUT
CXIF
CXVL
CXVM
DOUTA
DOUTB
FREF
FS
GNDH
GNDI
GNDL
GNDP
GNDT
IFIN
IOUTL
LON
LOP
PE
SYNCB
VDDD_DIGITAL_1
VDDH-DIG.INTERFACE
VDDL-LO
VDDP-LO_PUMP_SUPPLY
VDDI-LNA/MIXER
TP18
VDDH
PE
R23
10k
⍀
R43
DNP
VDDH
1
2
3
4
SW2
AGND; 5
TP15
TP16
TP17
TP19
C16
DNP
C26
100nF
C27
1nF
C28
100nF
J2
IF IN
C30
VAL C31
VAL
C99
VAL
C36
DNP
L1
10UH
NOTE: THESE 5 DEVICES ARE NOT DEFINED (CAPS OR INDUCTORS)
C24
10nF
C60
DNP
+
TP23
TP24
C25
100pF
C23
100pF
R18
100k
⍀
C21
DNP
VCM
TP25
R47
0
⍀
C15
2.2nF
TP2 TP1
TP11
TP10
C78
100pF
C77
100pF
MXOP
MXON
C43
DNP C22
180pF
L2
10UH
A B
1
2
3
JP22
R1
50
⍀
VDDI
T2
6
S
5
4
P
1
2
3
ADT1-1WT
R2
50
⍀
C38
0.1
␮
F
VDDI
J3
MIXER OUTPUT
ADC IN
C37
DNP
Figure 6a. AD9874 Interface
AGND; 3, 4, 5
T3
6
S
J6
CLKIN
5
4
P
1
2
3
ADT1-6T
1
2
C62
VAL
C63
VAL R30
VAL
R31
VAL
A
B
1
2
3
JP18
R33
549
⍀
R32
549
⍀
TP3
IOUTC
VREGPQ
3
2
3
D5
1SV228
1
D5
1SV228
C29
VAL
C33
VAL
L12
100UH
R3
0
⍀
R4
0
⍀
CLKP
CLKN
C41
0.01
␮
F
C42
0.01
␮
F
MATCH LENGTH
VOLTAGE CONTROLLED OSCILLATOR
R58
0
⍀
R25
100
⍀
R26
0
⍀
R57
0
⍀
R27
0
⍀
CLKIN
R52
0
⍀
VDDC
CLOCK SYNTHESIZER INTERFACE
AGND; 3, 4, 5
LOIN
T1
4
S
J5
5
6
P
3
2
1
ADT1-1WT
1
2
M1
VCOMODULE
35 36 37 38 39 40 41 42 43 44
1
2
3
4
5
6
7
8
9
10
11
12
22 21 20 19 18 17 16 15 14 13
34
33
32
31
30
29
28
27
26
25
24
23
VCOVDD
VIN
CLKOUT
VDD
R62
0
⍀
R60
0
⍀
R61
200
⍀
MATCH LENGTH
R59
0
⍀
C65
0.1
␮
F
C64
0.1
␮
F
R63
0
⍀
R50
VAL
LON
R48
VAL
LOP
R49
VAL
VDDI
C44
VAL C66
VAL C67
VAL
R36
VAL
R37
VAL
HIGH IMPEDANCE
A
B
1
2
3
JP15
R35
549
⍀
R34
549
⍀
TP4
IOUTL
VREGPQ
LO SYNTHESIZER INTERFACE
Figure 6b. CLK and LO Ext. Input/Synthesizer Interface