AMD Vega 10, Справочник данных

Страница: 63 / 188

4.4 LCD Panel Power-up/down Timing (eDP Interface)
Figure 4–5 eDP Panel Power-up/down Timing
Note: The Aux CH response from sink is dependent on the application of LCDVCC.
Table 4–3 Registers for Setting Backlight PWM Parameters
Parameter Description Time (ms)
T1+T2
Power rail rise time from 10% to 90% and delay from LCDVDCC to
black video generation Hardware controlled,
up to 210 ms
T3 Delay from LCDVCC active to HPD high and Aux Software controlled
T4 Delay from HPD high to link training initialization Software controlled
T8 Delay from “Valid Video Data” to ENA_BL/VARY_BL active Software controlled
T9
Delay from ENA_BL/VARY_BL inactive to the end of “Valid Video
Data”
Software controlled
T10
Delay from “Source Main-Link Data” off to LCDVCC Off Software controlled
T11 Power rail fall time from 90% to 10%
Hardware controlled,
up to 10 ms
T12
Minimum panel off duration (off time is ≥ T12) Software controlled
Timing Specifications 51
© 2017 Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
"Vega 10" Databook
56006_1.00