AMD Vega 10, Справочник данных

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4
Timing Specifications
This chapter describes bus and memory timing specifications of "Vega 10".
To link to a topic of interest, use the following list of linked cross-references:
• SMBus Timing (p. 43)
• Initialization Sequence and Timing (p. 47)
• Serial Flash Read/Write Timing (p. 50)
• LCD Panel Power-up/down Timing (eDP Interface) (p. 51)
• LCD Panel Backlight Control with PWM (p. 52)
4.1 SMBus Timing
4.1.1 SMBus Write Cycle
The following figure shows an SRBM (system register bus manager) write cycle on
the SMBus interface.
Figure 4–1 SMBus Write Cycle
A typical SMBus write cycle consists of the following steps:
1. Issuing a Load Address Command to the SMB_ADDR register:
a. The SMBus master issues a START bit to the slave.
b. The SMBus master issues 7-bit slave address to the slave.
c. The SMBus master issues a write bit to the slave.
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