System Test and Debugging
24-10
Élan™SC520 Microcontroller User’s Manual
24.4.3
Other Debugging Features on the Élan™SC520 Microcontroller
24.4.3.1
Nonconcurrent Arbitration Mode
The ÉlanSC520 microcontroller’s system arbitration is comprised of an Am5
x
86 CPU bus
arbiter and a PCI bus arbiter, which enables concurrent mode operation. In the concurrent
arbitration mode, transactions on the Am5
x
86 CPU bus and the PCI bus can occur
simultaneously. For example, a peer-to-peer PCI bus transaction can occur simultaneously
with an Am5
x
86 CPU transaction. The advantage of this mode is the optimal utilization of
the two buses. However, this can be confusing when attempting system debugging,
because it is difficult to trace bus activity with concurrency. Also, some system bugs can
be traced back to improper configuration during concurrent arbitration mode while both the
Am5
x
86 CPU and external PCI bus masters are active. This occurs, for example, when the
Am5
x
86 CPU is modifying configuration registers such as address decode registers that
affect PCI bus master operation. In this case, using nonconcurrent arbitration mode instead
can assist in tracing these problems.
At system initialization, the ÉlanSC520 microcontroller boots up in the nonconcurrent
arbitration mode until the CNCR_MODE_ENB bit in the System Arbiter Control
(SYSARBCTL) register (MMCR offset 70h) is set. For debugging purposes, it can be useful
to omit this step and remain in nonconcurrent arbitration mode. For more details, see
Chapter 8, “System Arbitration”.
24.4.3.2
Echoing Integrated Peripheral Accesses on the GP Bus
All accesses from the Am5
x
86 CPU to the ÉlanSC520 microcontroller’s integrated
peripherals are not externally visible, but can optionally be directly monitored on the GP
bus using GP bus echo mode. If required, a logic analyzer can be connected to the GP bus
to monitor and debug the transactions. When the GP_ECHO_ENB
bit is set in the GP Echo
Mode (GPECHO) register (MMCR offset C00h), accesses to the GP-DMA controller, RTC,
internal timers, PIC, UARTs, and PIOs are echoed externally on the GP bus. During reads,
the data from the peripheral is also driven on the GP bus data lines, GPD15–GPD0.
24.4.3.3
Summary of Additional System Debugging Features
There are additional features in the ÉlanSC520 microcontroller that are not included
specifically for system debugging but can be useful during the debugging phase. These
features are described in other chapters, but are summarized below for reference.
■
The ÉlanSC520 microcontroller provides the ability to control the Am5
x
86 CPU’s cache
write policy with the Am5
x
86 CPU Control (CPUCTL) register (MMCR offset 02h) and
to disable the cache using the CPU’s machine status (CR0) register. This can be useful
in debugging some system problems when cache coherency is a problem or when
visibility of all Am5
x
86 CPU memory cycles are required externally. See Chapter 7,
“Am5x86® CPU”, for details on cache control.
■
The ÉlanSC520 microcontroller provides the ability to dynamically control the Am5
x
86
CPU’s internal clock speed in the Am5
x
86 CPU Control (CPUCTL) register. This is
primarily to allow thermal management, but there may be some cases when it is useful
to adjust the clock speed for debugging purposes. See Chapter 7, “Am5x86® CPU”, for
details on clock speed control.
■
The SDRAM controller’s write buffer and read buffer can be disabled by resetting the
WB_ENB bit in the SDRAM Buffer Control (DBCTL) register (MMCR offset 40h). This
can be useful during system debugging, because it prevents queued SDRAM writes and
prefetching on the SDRAM interface that can make it difficult to trace bus activity. See
Chapter 11, “Write Buffer and Read Buffer”, for details on disabling these features.
Содержание Elan SC520
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Страница 28: ...Introduction xxviii lan SC520 Microcontroller User s Manual...
Страница 42: ...Architectural Overview 1 14 lan SC520 Microcontroller User s Manual...
Страница 78: ...System Initialization 3 22 lan SC520 Microcontroller User s Manual...
Страница 108: ...Clock Generation and Control 5 10 lan SC520 Microcontroller User s Manual...
Страница 118: ...Reset Generation 6 10 lan SC520 Microcontroller User s Manual...
Страница 148: ...System Arbitration 8 24 lan SC520 Microcontroller User s Manual...
Страница 214: ...SDRAM Controller 10 36 lan SC520 Microcontroller User s Manual...
Страница 230: ...Write Buffer and Read Buffer 11 16 lan SC520 Microcontroller User s Manual...
Страница 288: ...GP Bus DMA Controller 14 22 lan SC520 Microcontroller User s Manual...
Страница 316: ...Programmable Interval Timer 16 8 lan SC520 Microcontroller User s Manual...
Страница 328: ...Software Timer 18 4 lan SC520 Microcontroller User s Manual...
Страница 346: ...Real Time Clock 20 12 lan SC520 Microcontroller User s Manual...
Страница 360: ...UART Serial Ports 21 14 lan SC520 Microcontroller User s Manual...
Страница 414: ...AMDebug Technology 26 8 lan SC520 Microcontroller User s Manual...