Chapter 6: Board Test System
6–5
Using the Board Test System
July 2012
Altera Corporation
Stratix V GX FPGA Development Kit
User Guide
■
PSS
—Displays the MAX V PSS register value. Refer to
Table 6–1
for the list of
available options.
■
PSR
—Sets the MAX V PSR register. The numerical values in the list corresponds
to the page of flash memory to load during FPGA reconfiguration. Refer to
Table 6–1
for more information.
1
Because the
System Info
tab requires that a specific design is running in the FPGA at
a specific clock speed, writing a 0 to SRST or changing the PSO value can cause the
Board Test System to stop running.
JTAG Chain
The
JTAG chain
control shows all the devices currently in the JTAG chain. The
Stratix V GX device is always the first device in the chain. The JTAG chain is normally
mastered by the On-board USB-Blaster II.
1
If you plug in an external USB-Blaster cable to the JTAG header (J10), the On Board
USB-Blaster II is disabled.
1
DIP switch SW3 selects which interfaces are in the chain. Set SW3 switch positions in
the off position to include the interface in the JTAG chain. Refer to
Table 4–2
for
detailed settings.
f
For details on the JTAG chain, refer to the
Stratix V GX FPGA Development Board
Reference Manual.
For USB-Blaster II configuration details, refer to the
On-Board
USB-Blaster II
page.
Qsys Memory Map
The
Qsys memory map
control shows the memory map of the Qsys system on your
board.
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