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Chapter 1: About This Kit

1–3

Kit Features

July 2012

Altera Corporation

Stratix V GX FPGA Development Kit

User Guide

■

Nios

II Embedded Design Suite (EDS)—A full-featured set of tools that allows

you to develop embedded software for the Nios II processor which you can
include in your Altera FPGA designs.

Stratix V GX FPGA Development Kit Installer

The license-free Stratix V GX FPGA Development Kit installer includes all the
documentation and design examples for the kit.

For information on installing the Development Kit Installer, refer to

“Software

Installation” on page 3–1

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Содержание Stratix V GX Edition

Страница 1: ...e San Jose CA 95134 www altera com UG 01103 1 2 User Guide Stratix V GX FPGA Development Kit Feedback Subscribe Stratix V GX FPGA Development Kit User Guide Downloaded from Elcodis com electronic comp...

Страница 2: ...fications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability ari...

Страница 3: ...pter 4 Development Board Setup Setting Up the Board 4 1 Factory Default Switch Settings 4 2 Chapter 5 Board Update Portal Connecting to the Board Update Portal Web Page 5 1 Using the Board Update Port...

Страница 4: ...s 6 13 Port 6 14 PMA Setting 6 14 Data Type 6 14 Error Control 6 15 Start 6 15 Stop 6 15 Performance Indicators 6 15 The XCVR2 Tab 6 16 Status 6 16 Port 6 17 PMA Setting 6 17 Data Type 6 17 Error Cont...

Страница 5: ...Flash Programming A 2 Creating Flash Files Using the Nios II EDS A 2 Programming Flash Memory Using the Board Update Portal A 3 Programming Flash Memory Using the Nios II EDS A 3 Restoring the Flash D...

Страница 6: ...vi Contents Stratix V GX FPGA Development Kit July 2012 Altera Corporation User Guide Downloaded from Elcodis com electronic components distributor...

Страница 7: ...e modular and scalable design by using the high speed mezzanine card HSMC connectors to interface to over 40 different HSMCs provided by Altera partners supporting protocols such as Serial RapidIO 10...

Страница 8: ...o Quartus II software For more information refer to the Design Software page of the Altera website The Quartus II Development Kit Edition DKE software includes the following items Quartus II Software...

Страница 9: ...oftware for the Nios II processor which you can include in your Altera FPGA designs Stratix V GX FPGA Development Kit Installer The license free Stratix V GX FPGA Development Kit installer includes al...

Страница 10: ...1 4 Chapter 1 About This Kit Kit Features Stratix V GX FPGA Development Kit July 2012 Altera Corporation User Guide Downloaded from Elcodis com electronic components distributor...

Страница 11: ...he board perform the following steps 1 Place the board on an anti static surface and inspect it to ensure that it has not been damaged during shipment c Without proper anti static handling you can dam...

Страница 12: ...A Development Kit page For additional daughter cards available for purchase refer to the Development Board Daughtercards page For the Stratix V GX device documentation refer to the Literature Stratix...

Страница 13: ...ntitles you to a one year license for the Development Kit Edition DKE of the Quartus II software 1 After the year your DKE license will no longer be valid and you will not be permitted to use this ver...

Страница 14: ...use to run the Quartus II software type ipconfig all at a command prompt to determine the NIC ID Your NIC ID is the 12 digit hexadecimal number on the Physical Address line 4 When licensing is comple...

Страница 15: ...the instructions f For USB Blaster II configuration details refer to the On Board USB Blaster II page Figure 3 1 Stratix V GX FPGA Development Kit Installed Directory Structure 1 Note to Figure 3 1 1...

Страница 16: ...Chapter 3 Software Installation Installing the USB Blaster II Driver Stratix V GX FPGA Development Kit July 2012 Altera Corporation User Guide Downloaded from Elcodis com electronic components distrib...

Страница 17: ...board 5 Ensure that the power switch SW2 is in the off position 6 Connect the Power Adpater 19 V 6 32 A to the DC Power Jack J4 on the FPGA board and plug the cord into a power outlet c Use only the...

Страница 18: ...settings for the Stratix V GX FPGA development board Figure 4 1 shows the switch locations and the default position of each switch on the top side of the board Figure 4 1 Switch Locations and Default...

Страница 19: ...d Figure 4 1 Figure 4 2 Switch Locations and Default Settings on the Board Bottom 4 3 2 1 ON MSEL 6 5 4 3 2 1 ON JTAG 4 3 2 1 SW5 ON 4 3 2 1 SW6 ON x1 x4 x8 SECURITY FACTORY CLK_EN CLK_SEL MAXV HSMA H...

Страница 20: ...udes the HSMC Port A from the JTAG chain On 3 HSMB_JTAG_EN Switch 3 has the following options When on 0 removes the HSMC Port B in the JTAG chain When off 1 includes the HSMC Port B from the JTAG chai...

Страница 21: ...formation on the Stratix V ES JTAG Port Access Limitation After Configuration refer to Errata Sheet and Guidelines for Stratix V ES Devices Table 4 4 SW5 DIP Switch Settings Switc h Board Label Functi...

Страница 22: ...tch Settings Switc h Board Label Function Default Position 1 PCIE_PRSNT2 n_x1 Switch 1 has the following options When on 0 x1 presence detect is enabled When off 1 x1 presence detect is disabled On 2...

Страница 23: ...te Portal design resides in the install dir kits stratixVGX_5sgxea7kf40_fpga examples directory If the Board Update Portal is corrupted or deleted from the flash memory refer to Restoring the Flash De...

Страница 24: ...the user portion of flash memory on your board perform the following steps 1 Perform the steps in Connecting to the Board Update Portal Web Page to access the Board Update Portal web page 2 In the Ha...

Страница 25: ...designs specific to the functionality you are testing The application is also useful as a reference for designing systems To install the application follow the steps in Installing the Stratix V GX FPG...

Страница 26: ...Settings section starting on page 4 2 except for DIP switch SW5 3 3 Set the DIP switch SW5 3 to the on user position f For more information about the board s DIP switch and jumper settings refer to th...

Страница 27: ...gn perform the following steps 1 On the Configure menu click the configure command that corresponds to the functionality you wish to test 2 When configuration finishes close the Quartus II Programmer...

Страница 28: ...rmation PSO Sets the MAX V PSO register The following options are available Use PSR Allows the PSR to determine the page of flash memory to use for FPGA reconfiguration Use PSS Allows the PSS to deter...

Страница 29: ...chain control shows all the devices currently in the JTAG chain The Stratix V GX device is always the first device in the chain The JTAG chain is normally mastered by the On board USB Blaster II 1 If...

Страница 30: ...ng sections describe the controls on the GPIO tab Character LCD The Character LCD control allows you to display text strings on the character LCD on your board Type text in the text boxes and then cli...

Страница 31: ...the graphical representation of the LEDs Push Button Switches The read only Push button switches control displays the current state of the board user push buttons Press a push button on the board to s...

Страница 32: ...back to guarantee that the graphical display accurately reflects the memory contents 1 To prevent overwriting the dedicated portions of flash memory the application limits the writable flash memory ad...

Страница 33: ...tart The Start control initiates DDR3 memory transaction performance analysis Stop The Stop control terminates transaction performance analysis Performance Indicators These controls display current tr...

Страница 34: ...mance analysis Clear Resets the Detected errors and Inserted errors counters to zeros Number of Addresses to Write and Read The Number of addresses to write and read control determines the number of a...

Страница 35: ...QDR II memory on your board and independently test each QDR II port Figure 6 6 shows the QDRII tab The following sections describe the controls on the QDRII tab Start The Start control initiates QDR...

Страница 36: ...5 MHz 4040 or 1100 Mbps per pin Changing the oscillator U46 CLK0 frequency to 100 MHz changes the circuit speed to 440 MHz or 880 Mbps per pin Typically you need to reset the QDR II design after chang...

Страница 37: ...ts to function in external loopback mode Otherwise set the PMA setting tab to test internal loopback mode serial loopback 1 The following sections describe the controls on the XCVR1 tab Status The Sta...

Страница 38: ...ternal loopback 2 Reverse serial loopback pre CDR 4 Reverse serial loopback post CDR VOD Specifies the voltage output differential of the transmitter buffer Pre emphasis tap Pre Specifies the amount o...

Страница 39: ...ransmit data stream each time you click the button Insert Error is only enabled during transaction performance analysis Clear Resets the Detected errors and Inserted errors counters to zeros Start The...

Страница 40: ...ctly Unless you have a QSFP loopback module you will need test the QSFP in the internal loopback mode serial loopback 1 The following sections describe the controls on the XCVR2 tab Status The Status...

Страница 41: ...R 4 Reverse serial loopback post CDR VOD Specifies the voltage output differential of the transmitter buffer Pre emphasis tap Pre Specifies the amount of pre emphasis on the pre tap of the transmitter...

Страница 42: ...click the button Insert Error is only enabled during transaction performance analysis Clear Resets the Detected errors and Inserted errors counters to zeros Start The Start control initiates the sele...

Страница 43: ...back adjust the setting using the PMA button serial loopback 1 The following sections describe the controls on the XCVR3 tab Status The Status control displays the following status information during...

Страница 44: ...sceiver signals to observe to 10G high speed transmit data signal 1 Serial loopback VOD Specifies the voltage output differential of the transmitter buffer Pre emphasis tap Pre Specifies the amount of...

Страница 45: ...nce analysis 1 Always click Clear before Start Stop The Stop control terminates transaction performance analysis Performance Indicators These controls display current transaction performance analysis...

Страница 46: ...ay the following information about the MAX V device MAX V version Indicates the version of MAX V code currently running on the board The MAX V code resides in the install dir kits stratixVGX_5sgxea7kf...

Страница 47: ...he look and feel of the power graph Scale select Specifies the amount to scale the power graph Select a smaller number to zoom in to see finer detail Select a larger number to zoom out to see the enti...

Страница 48: ...FPGA development board s clocking circuitry and clock input pins refer to the Stratix V GX FPGA Development Board Reference Manual The Clock Control communicates with the MAX V device on the board th...

Страница 49: ...r and the USB Blaster II driver are installed on the host computer the micro USB cable is connected to the FPGA development board power to the board is on and no other applications that use the JTAG c...

Страница 50: ...r 6 Board Test System Configuring the FPGA Using the Quartus II Programmer Stratix V GX FPGA Development Kit July 2012 Altera Corporation User Guide Downloaded from Elcodis com electronic components d...

Страница 51: ...design was created using the Quartus II software f For more information about Altera development tools refer to the Design Software page of the Altera website CFI Flash Memory Map Table A 1 shows the...

Страница 52: ...or more information about Nios II EDS software tools and practices refer to the Embedded Software Development page of the Altera website Creating Flash Files Using the Nios II EDS If you have an FPGA...

Страница 53: ...e Config Done LED D17 does not illuminate continue to step 4 to load the FPGA with a flash writing design 4 Launch the Quartus II Programmer to configure the FPGA with a sof capable of flash programmi...

Страница 54: ...uration is complete when the progress bar reaches 100 The Config Done LED D17 illuminates indicating that the flash device is ready for programming The flash device is ready for programming 6 On the W...

Страница 55: ...ts to the MAX V CPLD on the FPGA development board Make sure you have the Nios II EDS installed and perform the following instructions 1 Set the board switches to the factory default settings describe...

Страница 56: ...gramming the Flash Memory Device Restoring the MAX V CPLD to the Factory Settings Stratix V GX FPGA Development Kit July 2012 Altera Corporation User Guide Downloaded from Elcodis com electronic compo...

Страница 57: ...om training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com software licensing Email authorization altera com Note t...

Страница 58: ...and a b c and so on Numbered steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets indicate a list of items when the sequence of th...

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