Altera Stratix V GX Edition, Руководство пользователя

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Chapter 6: Board Test System 6–13
Using the Board Test System
July 2012 Altera Corporation Stratix V GX FPGA Development Kit
User Guide
The XCVR1 Tab
The XCVR1 tab allows you to perform loopback tests on the SDI and HSMA
Transceivers, HSMA LVDS, and HSMA CMOS Parallel interfaces. Figure 6–7 shows
the XCVR1 tab.
1
You must have the loopback HSMC installed on the HSMC connector Port A and the
SDI loopback cable for all tests to function in external loopback mode. Otherwise, set
the PMA setting tab to test internal loopback mode (serial loopback = 1).
The following sections describe the controls on the XCVR1 tab.
Status
The Status control displays the following status information during the loopback test:
■ PLL lock —Shows the PLL locked or unlocked state.
■
Channel lock —Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded, and all TX and RX PLL lanes are
phase locked to data; RX lanes are word aligned and deskewed.
Figure 6–7. The XCVR1 Tab
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