ZYNQ Ultr FPGA Board AXU5EV-P User Manual
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need to choose PCIE type SSD solid state drives.
The PCIE signal is directly connected to the BANK505 PS MGT
transceiver of ZU5EV, and the TX signal and RX signal of one channel are
connected to the LANE1 of MGT in a differential signal mode. The PCIE clock
is provided by the Si5332 chip, the frequency is 100Mhz, and the schematic
diagram of the M.2 circuit design is shown in Figure 3-2-1:
Figure 3-2-1: M.2 Interface Schematic
The pin assignment of M.2 interface ZYNQ is as follows:
Signal Name
Pin Name
Pin Number
Description
PCIE_TX_P
505_TX0_P
E25
PCIE Data Transmit Positive
PCIE _TX_N
505_TX0_N
E26
PCIE Data Transmit Negative
PCIE _RX_P
505_RX0_P
F27
PCIE Data Receive Positive
PCIE _RX_N
505_RX0_N
F28
PCIE Data Receive Negative
505_PCIE_REFCLK_P
505_CLK0_P
F23
PCIE Reference Clock Positive
505_PCIE_REFCLK_N
505_CLK0_N
F24
PCIE Reference Clock Negative
PCIE_RSTn_MIO37
PS_MIO37_501
J17
PCIE Reset Signal
Part 3.3: DP Interface
The AXU5EV-P development board has a standard DisplayPort output
display interface for video image display. The interface supports VESA
