ZYNQ Ultr FPGA Board AXU5EV-P User Manual
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Part 2.6: Clock configuration
The core board provides reference clock and RTC real-time clock for PS
system and PL logic respectively, so that PS system and PL logic can work
independently. The schematic diagram of the clock circuit design is shown in
Figure 2-6-1:
Figure 2-6-1: Core Board Clock Source
PS System RTC Real Time Clock
The passive crystal Y2 on the core board provides a 32.768KHz real-time
clock source for the PS system. The crystal is connected to the PS_PADI_503
and PS_PADO_503 pins of BANK503 of the ZYNQ chip. The schematic
diagram is shown in Figure 2-6-2:
Figure 2-6-2: Passive Crystal Oscillator for RTC
