Alesis QUADRAVERB, Руководство по обслуживанию

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Alesis QuadraVerb Service Manual------ 5 08/13/04
4.3 Memory Mapped I/O
The QuadraVerb (and many other Alesis products) utilizes a memory mapped I/O system in
order to deal with the wide variety of functions that the 8031 needs to access. During the write cycle
of the 8031, data on the 8031 data buss is made available to a series of latches. When the WRN (pin
16) signal of the 8031 is enabled, and A15 (address's most significant bit) is active, the 3 to 8 line
demux (U23) is used to decode the 3 least significant address lines, and send a strobe to the clock
input of one of these latches. Consequently, data can be "stored" into a latch simply by writing a
value into a memory location. Note that, in this scenario, data is write only. All input functions to the
8031 are handled through the 8031's built in I/O ports.
4.4 Analog Input and the 8031
While output from the 8031 can be handled simply using memory mapped I/O, and binary
weighted networks, analog input to the 8031 is a bit trickier. The method used in the QuadraVerb, is
to examine the time it takes a constantly charging capacitor to reach the level of the input signal. The
majority of op amp U22 is used to accomplish this. We will examine the audio threshold input. The
principle will also apply to the piezo (Z2) value input circuit.
The process begins with the 8031 temporarily turning on Q2 (via mapped I/O latch U29). After
turning Q2 back off, the 8031 begins counting. While the 8031 is counting, C56 charges through
R51. This signal is compared to the incoming rectified analog signal (from the LED control circuit) by
U22 (pins 5, 6, and 7). When the charge on C56 reaches the level of the input signal, U22 pin 7 will
change states, informing the 8031 via input port P3.2. The 8031 ceases counting, and can use the
"count" value as a "level" value for processing.
4.5 DASP 24 ASIC
The DASP (Digital Audio Signal Processor) 24 ASIC (Application Specific Integrated Circuit),
is a complex, VLSI IC designed specifically to handle the specialized needs of digital effects
processing. Obviously, a full discussion of this device is beyond the scope of this manual, however, a
brief introduction to the device is definitely in order.
The DASP 24 contains a SAR (Successive Approximation Register), a writable control store
(internal memory for algorithm storage), and a RISC (Reduced Instruction Set Computer) for use as
an Arithmetic Logic Unit. Memory management hardware, and a variety of control hardware round
out the package. Some important control signals are outlined below.