Alesis QUADRAVERB, Руководство по обслуживанию

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Alesis QuadraVerb Service Manual------ 4 08/13/04
comparison are stored, and the next most significant bit is compared. This process continues until a
value is found for all 16 bits, and the data is ready for further processing by the ASIC (note that the
value is in two's compliment math). In order to view these signals properly on the scope, it will be
necessary to use an external scope sync (use U9, pin 9 as the sync source). Diagrams 2, and 3,
show the DAC output during a couple of SAR cycles, with no input, and full input.
4.0 Digital Signal Paths
Note that later board revisions incorporate a "split" data buss. In other words, most "external"
data lines are separated from the main buss via a de coupling network (R35, R84-90, C28-30, C35-
37, C42, C44). This is to provide better RF suppression, however, it can also cause some unique
situations. Normal signals on this "secondary" buss, will appear extremely distorted (for digital
signals), and sometimes lead a technician to believe that there may be a bad latch, even though all
components on the buss are functioning properly. Conversely, a bad latch can load the buss in such
a way, that bad timing occurs, corrupting data even though the signals appear "normal".
4.1 80C31 Micro Controller Circuit
The 80C31 MPU controls all "user interface" functions of the QuadraVerb. These functions
range from handling the front panel buttons, to continuously updating algorithm information to the
DASP 24 ASIC. Note that the 8031 data buss serves a dual purpose. This buss multiplexes between
low order addresses (1st 8 bits), and data. Latch U20 is used to hold the low order address half,
during 8031 read and write cycles. The EPROM (U19) is used to hold both program information, and
algorithm data. The SRAM (U18) holds system variables, as well as user preset data. The 12MHz
8031 clock is derived from the 24MHz clock (Z1) via a divide by 2 counter (1/2 U24). MIDI I/O is
handled through the 8031's built in RXD (Read Serial Data), and TXD (Transmit Serial Data) ports.
Front panel keypad decoding is handled through a combination of memory mapped I/O (see section
4.3), and the 8031's built in I/O ports.
4.2 Reset
The 8031 reset circuit is perhaps the single most important circuit in the QuadraVerb. When
this circuit is functioning incorrectly, problems ranging from loss of battery backup, to a complete
lock-up of the machine, can occur. A thorough knowledge of the operation of this circuit will greatly
facilitate troubleshooting this unit.
This circuit uses the differential between raw +10V, and reg5V, to generate the
required signals for system reset. This is necessary due to fact that the system MUST be in a reset
state while powering down, otherwise, random noise on the 8031 data, and address, busses could
corrupt SRAM data, and destroy any hope that the battery backup will work. C25 acts as a long time
constant, to ensure that reset line is enabled long enough for proper system reset. D7 acts as a
quick discharge path for C25, ensuring that resets will occur, even if the unit is turned off, and then
rapidly back on. R16, R60, R58, and D15, work together as a voltage divider to the base of Q3, and
is designed so that transistor Q3 will turn on when the raw +10V supply is roughly 7V. This is to
ensure that reset does not occur until after the +5V regulator is fully functioning (i.e. +5V rail is solid).
If reset occurs too early, noise on the +5V rail can cause data corruption. Pull-up resistor R59 holds
the input of the inverter (U25, pins 13, 12) high, until Q3 turns on, pulling the input low. When this
occurs, the output of 2nd inverter (U25 pins 10, 11) will also go low, slowly, due to the time constant
of R95, and C32. The power off reset is similar. When the +10V raw supply sinks below 7V, Q3 is
turned off, allowing the input of the inverter (U25, pins 13,12) to pull high (via pull-up R59), and thus
the same for the output of the 2nd inverter (U25, pins 10,11). Also note the tap between the two
inverters, running to the input of AND gate U26 (pins 1,2, and 3). This prevents access to SRAM
functions while in the reset condition, thus preventing data corruption.