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[AKD4396-SBW]
<KM078103> 4 2011/03
The frequency of the master clock output is set by OCKS0 and OCKS1 as shown in Table 4
.
OCKS1 OCKS0
MCLK
Frequency
0 0
256fs
@fs=88.2/96kHz
1 0
512fs
@32/44.1/48kHz
1 1
128fs
@176.4/192kHz
Default
Table 4 MCLK Clock
SW1 setting
[SW1](PDN): Reset of AK4396. Select “H” during operation
.
External Analog Circuit
The differential output circuit and LPF is implemented on board. The differential outputs of AK4396 is buffered by non-inverted circuit
(2
nd
order LPF, fc=182k, Q=0.637, G=+3.9dB)
. LPF adds differential outputs
(1
st
order LPF, fc=284k, G=-0.84dB)
. NJM5534D is used for
op-amp on this board that has low noise and high voltage torelance characteristics. Analog signal is output via BNC connectors on the board.
The output level is about 2.8Vrms (typ@VREF=5.0V) by BNC.
330
100u
180
AOUTL-
10
k
3.9n
1.
2k
680
3.3n
6
4
3
2
7
10u
0.1u
0.1u
10u
10u
NJM5534D
330
100u
180
AOUTL+
10
k
3.9n
1.
2k
680
3.3n
6
4
3
2
7
10u
0.1u
0.1u
10u
NJM5534D
0.1u
+
NJM5534D
0.1u
10u
100
4
3
2
1.0n
620
620
560
7
+
+
+
+
-
+
-
+
+
+
-
+
+
1.0n
Lch
-15
+15
6
5
60
Figure 4
External Analog Filter
AKD4396-SBW
Filter
40kHz (Double)
80kHz (quad)
Internal Filter
-0.3dB
-1dB
External LPF
-0.19dB
-0.85dB
Total -0.49dB
-1.85dB
This table shows typical value.
Table 5 Frequency Responses