-26-
Pin No.
Pin Name
I/O
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
TE
_______
POR
12CC
12CD
VDD
VSS
DCEN
_______
EOD
_______
RTR
_________
RTW
DCSG
DCSO
VSENS
PR
_______
PCS
PI19
PI18
PI17
PI16
PI15
PI14
PI13
PI12
SOD
SOI
SOC
P18
XVDD
XVSS
SID
SII
SIC
PI4
I
I
I/O
I/O
–
–
I
O
O
O
–
O
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I/O
–
–
I
I
I
I/O
Test enable
Reset, active “L”
I
2
C clock low
I
2
C data line
Positive supply for digital parts
Ground supply for digital parts
Enable DC/DCconverter
PIO end of DMA, active “L”
PIO ready to read, active “L”
PIO ready to write, active “L”
DC converter transistor ground
DC converter transistor open drain
DC converter voltage sense
____
PIO-DMA request or read/write
PIO chip select, active “L”
PIO data [19] 1. Demand pin in SDI mode 2. data bit [7], MSB (PIO-DMA input mode)
PIO data [18] 1. MPEG header bit 11-MPEG ID (SDI mode)
2. data bit [6] (PIO-DMA input mode)
PIO data [17] 1. MPEG header bit 12-MPEG ID (SDI mode)
2. data bit [5] (PIO-DMA input mode)
PIO data [16] 1. SIC, alternative input for SIC (SDI mode)
2. data bit [4] (PIO-DMA input mode)
PIO data [15] 1. SII, alternative input for SII (SDI mode)
2. data bit [3] (PIO-DMA input mode)
PIO data [14] 1. SID, alternative input for SID (SDI mode)
2. data bit [2] (PIO-DMA input mode)
PIO data [13] 1. MPEG header bit 13-Layer ID (SDI mode)
2. data bit [1] (PIO-DMA input mode)
PIO data [12] 1. MPEG header bit 14-Layer ID (SDI mode)
2. data bit [0] (PIO-DMA input mode)
Serial output data
Serial output frame identification
Serial output clock
Start-up 1): clock output scaler ON/OFF, Operation 2): MPEG CRC error
Positive supply of output buffers
Ground of output buffers
Serial input data
Serial input frame identification
Serial input clock
Start-up 1): Select SDI/PIO-DMA input mode, Operation 2): MPEG frame sync
IC DESCRIPTION - 3/6 (MAS3507D-G10) - 1/2
