-23-
Pin No.
Pin Name
I/O
Description
35
36
37
38
39
40
41
42
43
44
45
46
47
48 〜 55
56 〜 63
64 〜 71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
DECRST
AVREF1
DEBUG1
DEBUG2
DEBUG3
̲̲̲̲̲̲̲̲̲̲̲̲̲
MP3ON
NC
̲̲̲̲̲̲̲
STNBY
̲
DSL1/2
BEEP
I
2
CD
A-MUTE
I
2
CC
A0 〜 A7
D0 〜 D7
A8 〜 A15
VSS
A16
̲̲̲̲
CS1
̲̲̲̲
CS2
̲̲̲̲
CS3
̲̲̲
RD
̲̲̲
WD
̲̲̲̲̲̲̲̲
MP3RST
ASTB
VDD
̲̲̲̲̲
DTEN
XCLK
XLAT
XDATA
PWM
SCLK
SENS
SQCK
SUBQ
XRST
SPCON
SLCON
VPP
NC
DSLON
O
─
I
O
O
O
─
O
O
O
I/O
O
I/O
O
I/O
O
─
O
O
O
O
O
O
O
─
─
I
O
O
O
O
O
I
O
I
O
O
O
─
─
O
IC DESCRIPTION - 1/6 (µPD784216AYGC-105-8EU) - 2/3
RESET output to ROM decoder
Connected to VDD since D/A converter is not used.
For debugging ("L" when hyper terminal is not used)
Data switching output. "H": CD-DA; "L": MP3
Not used
Standby output to H.PAMP. "H": ON; "L": STANDBY
DSL1/2 switching output. "H": DSL1; "L": DSL2
BEEP output to H.PAMP
I
2
C DATA
MUTE output to H.PAMP. "H": MUTE
I
2
C CLOCK
Address bus
Data bus
Address bus
GND
Address bus
CS output to external RAM
CS output to ROM decoder
CS output to LCD driver
Strobe signal output to external RAM and ROM decoder for reading
Strobe signal output to external RAM and ROM decoder for writing
RESET output to MP3 decoder
Not used
Power supply
Data enable input from ROM decoder
Clock output for serial data transfer to DSP
Latch output for serial data transfer to DSP
Serial data output to DSP
PWM output for spindle rotation during EASS intermittent processing
Clock output to DSP for reading SENS data
SENS data input from DSP
Clock output to DSP for reading SUBQ
SUBQ data input from DSP
CD system reset output
Spindle control pulse output
Sled control pulse output
High voltage is applied to write data to flash memory
Not used
DSL ON/OFF output to H.PAMP. "H": ON; "L": OFF
