36
MUTE
DEEM
CKO
DVSS
BCKI
DI
DVDD
LRCI
TSTN
TO1
AVDDL
LO
AVSS
RO
AVDDR
MUTEO
XVDD
XTI
XTO
XVSS
DS
RSTN
MODE
ATCK
IC, SM5878AN
Pin No.
Pin Name
I/O
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I
I
O
—
I
I
—
I
I
O
—
O
—
O
—
O
—
I
O
—
I
I
I
I
MODE = H: Soft mute ON/OFF terminal. (Mute at H).
MODE = L: Attenuator level DOWN/UP terminal. (DOWN at H).
De-emphasis ON/OFF terminal. (De-emphasis ON at H).
Oscillator clock output. (16.9344 MHz).
Digital VSS terminal.
Bit clock input terminal.
Serial data input terminal.
Digital VDD terminal.
Sample rate clock (fs) input terminal. (H = L ch/L = R ch).
Test input. (“H” or open during normal operation)
Test output 1. (Normally low level output).
Analog VDD terminal. (For L ch).
Left channel analog output terminal.
Analog VSS terminal.
Right channel analog output terminal.
Analog VDD terminal. (For R ch).
Infinity zero detection output.
X’tal system VDD terminal.
X’tal oscillator terminal. (Or external clock input terminal of 16.9344 MHz).
X’tal oscillator terminal.
X’tal system VSS terminal.
Double-speed/normal playback selection. (Double-speed at H).
Reset terminal. (Reset at L).
Soft mute/Attenuator mode selection. (Soft mute at H).
Attenuator level setup clock (Ignored when MODE = H).
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9
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2
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4
2
9
8
0
5
1
5
1
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6
7
3
Q
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