25
Bit 7 - Power On. Set when power is first applied to the instrument.
Bit 6 - Not used.
Bit 5 - Command Error. Set when a syntax type error is detected in a command from the bus.
The parser is reset and parsing continues at the next byte in the input stream.
Bit 4 - Execution Error. Set when an error is encountered while attempting to execute a
completely parsed command. The appropriate error number will be reported in the
Execution Error Register, see Error Messages section.
Bit 3 - Verify Timeout Error. Set when a parameter is set with 'verify' specified and the value is
not reached within 5 secs, e.g. output voltage is slowed by a large capacitor on the output.
Bit 2 - Query Error. Set when a query error occurs. The appropriate error number will be
reported in the Query Error Register.
Bit 1 - Not used.
Bit 0 - Operation Complete: Set in response to the ‘*OPC’ command.
Execution Error Register
This register contains a number representing the last error encountered over the current
interface. The Execution Error Register is read and cleared using the ‘EER?’ command. On
power up this register is set to 0 for all interface instances.
Error messages have the following meaning:
0
No error encountered.
1- 9
Indicates a hardware error has been encountered.
100
The numerical value sent with the command was too big or too small. Includes negative
numbers, illegal store numbers, numbers >1 where only 0 and 1 are allowed, etc.
101
A recall of set up data has been requested but the store specified contains corrupted data.
This indicates either a hardware fault or a temporary data corruption which can be corrected
by writing data to the store again.
102
A recall of set up data has been requested but the store specified does not contain any data.
103
Attempt to read or write a command on the second output. The unit is single output only.
200
Read Only: An attempt has been made to change the instruments settings from an interface
without write privileges. See ‘Interface Locking’ section for details
Limit Event Status and Limit Event Status Enable Registers
These two registers are implemented as an addition to the IEEE Std.488.2. Their purpose is to
inform the controller of entry to and/or exit from current or voltage limit conditions and the history
of protection trip conditions since the last read.
Any bits set in the Limit Event Status Register which corresponds to bits set in the Limit Event
Status Enable Register will cause the LIM1 bit to be set in the Status Byte Register.
The Limit Event Status Register is read and cleared by the LSR1? command. The Limit Event
Status Enable Register is set by the LSE1 <
NRF
> command and read by the LSE1? command.
