PCI-1241/1242 User Manual
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B.3 Close Loop Motion Control (Velocity Command)
The PC Controller sends commands to the PCI BUS interface circuit (4)
on the PCI-1241/1242 card through PCI BUS (1). At this time, the com-
mand and state register (5) with system control circuit (8) will decode
commands and enable DDA generator (9) in the driver to send out pulses
evenly (selectable to A/B PHASE, CW/CCW, and the PC Controller
sends commands to the PCI BUS interface circuit (4) on the PCI-1241
card through PCI BUS (1).
At this time, the ASIC will decode commands and direct the DDA gener-
ator (9) in the driver to send out pulses evenly. The pulses are then sent to
the close loop mechanism (13). At the same time, the feedback signal of
motor encoder (18) (in the form of a differential drive) enters PCI-1241
through a connector. It goes through photo coupler isolation (20) module
and enters into the encoder interface (19) for signal processing (including
filtering).
The signal then enters close loop mechanism (13) for calculation. The
close loop mechanism (13) uses a proportional control algorithm (Figure
B-3 shows P-type control method in close loop control) to produce veloc-
ity command for driving DAC module (16) via DAC interface (14). The
voltage commands are produced by multiplying a gain on the difference
of pulses sent by DDA and pulses be feed backed by encoder. Finally,
voltage command (–10V ~ +10V) is sent to velocity-type servo motor
(17) through connector.
Each set of close loop voltage output control is provided with a set of D/A
converter outputs and a set of encoder inputs. When the set of close loop
voltage output control is not used, the D/A converter can be spared for
CPU’s use to output voltage signal. In addition, encoder input can also be
connected to other encoders or MPG and read by CPU for encoder values.
If there four sets of close loop voltage output control are used, then four
sets of D/A and four sets of encoder input are allocated for close loop
control and no longer available for CPU use alone.
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Страница 81: ...2 APPENDIX B Block Diagram This chapter provides information on the block diagram for PCI 1241 1242...
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